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JPS6281175A Expired / Lapsed JP ⏱️ 0.0 years remaining

Horizontal sync signal regeneration circuit

Assignee: Seiko Epson Corp
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Filing: 1985-10-03
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Granted: —
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Expires: 2005-10-03
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Abstract

Abstract PURPOSE:To remove distortion in display picture by using a phase controlled oscillator in separating a horizontal synchronizing signal from a composite synchronizing signal, making said oscillation oscillate autonomously at the ending time of one frame of scanning, and thereby generating the horizontal synchronizing signal having a continuity with a horizontal scanning period. CONSTITUTION:From a synchronizing signal separating circuit 1, the composite synchronizing signal is inputted to a J-KFF 3 through an inverter 4. The J-KFF 7 outputs an ending signal and turns on a gate 10. A PLL is formed with a phase comparator 9, a voltage controlled oscillator 12, and a frequency divider 13. The oscillator 12 outputs a pulse signal that has the same timing as that of the Q1-terminal-output of the FF 3 i.e. an ending-timing corresponding with the leading edge of a horizontal synchronizing signal, and outputs said signal to a terminal 14 as a horizontal synchronizing signal. When the FF 3 is reset during a period when vertical synchronizing signals are being outputted and after the last horizontal synchronizing signal in a frame is inputted, an FF 7 outputs a high-level signal to turn off the gate 10, when the oscillator 12 operates autonomously based on the voltage of a voltage holding circuit 11, so that the oscillation is continued with a period approximately coinciding with that of a horizontal synchronizing signal.

Inventors

  • 👤 Yoshiji Kimura
  • 👤 佳司 木村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 19:53
CPC Classifications
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