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JPS63136232A Expired / Lapsed JP ⏱️ 0.0 years remaining

Information processor

Assignee: Sharp Corp
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Filing: 1986-11-28
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Granted: —
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Expires: 2006-11-28
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Abstract

Abstract PURPOSE:To improve the performance of an arithmetic processing part up to a 100%-level by inputting a data packed after allocating it to plural program memory parts and providing the routes for individual connection between each program memory part and a paired data detecting part. CONSTITUTION:An allocating part 25 allocates the data packet outputted from an arithmetic processing part 24 to two program memory parts 21 and 22. Thus both parts 21 and 22 receive inputs with 1/2 rate of the maximum performance. If the parallel processing programs are executed, the parts 21 and 22 perform data copies 40 and 41 respectively and the flow rates of two routes 26 and 27 are set a '1' respectively. Thus the flow rate '1' is attained with an output route 28 since a paired data detecting part 23 receives input of the flow rate '1' from both inputs. In other words, the maximum performance of the flow rate is secured up to a route 29. Therefore the performance of the part 24 can be improved up to a 100%-level and the parallel processing effect doubled.

Inventors

  • 👤 Toshiya Okamoto
  • 👤 俊弥 岡本
  • 👤 Shinichi Yoshida
  • 👤 芳田 真一

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:12
CPC Classifications
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References Cited (Backward Citations)

JPS57143641A Cited
JPS61201338A Cited

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