Control system for bypass buffer in cache memory controller

Abstract

Abstract PURPOSE:To speed up a storing processing by executing a storing processing against a bypass buffer (BB) in case a block including the target address of the request-to-store is stored in said BB at the time of issuing said request. CONSTITUTION:At the time of issuing a read-request for a data stored in the BB 51, if a store-waiting-flag for the BB that is stored in the entry of a bypass control buffer 50 corresponding to the address of the read-request is ON, the said read-request is made wait, but in case said flag is OFF, the data is read from the BB 51 and returned to the source of the request. Accordingly, if the block that includes the address of the processing currently executed and that which includes the target address of a read-request are the same, the read- processing is immediately executed only if the addresses are different. In case a block including the target address of the request-to-store is stored in the BB 51, the storing processing is directly executed against the BB 51 by a storing processing means. In such a way, the storing processing is made faster.

Inventors

• 👤 Kozo Yamano
• 👤 山野　孝三
• 👤 Yoichi Sato
• 👤 洋一 佐藤

Bibliographic Details