Multiprocessor system

Abstract

Abstract PURPOSE:To easily design a software by detecting that the abnormal condition of a slave processor is generated with the output of the data of a prescribed value to the data bus of a common memory. CONSTITUTION:A timer 11 set by a slave processor in a prescribed period, a logical gate 12 to control a covalent memory 1 to an impossible condition for reading and writing at the time-out time of the timer 11 and a resistance 13 to set the data output at a prescribed value when the common memory 1 is in the impossible condition for reading and writing are equipped. When a data output obtained by an access to the common memory 1 is a prescribed value a master processor detects it as a slave processor abnormality. Namely, when an abnormality is generated in the slave processor, a time-out is obtained without resetting the timer and an access to the common memory is executed by the master processor to data transmitting and receiving as needed. However, the common memory is controlled to the impossible condition for reading and writing. Accordingly, to detect the abnormality of the slave processor, it is not necessary to provide a special input and output gate and a software is easily designed.

Inventors

• 👤 Takayuki Koshi

Bibliographic Details