← Back to Patent Explorer
JPS647397A Expired / Lapsed JP ⏱️ 0.0 years remaining

Nonvolatile semiconductor memory

Assignee: Toshiba Corp
•
Filing: 1987-06-30
•
Granted: —
•
Expires: 2007-06-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To make a chip size small by connecting plural memory cells each comprising a MOSFET of floating gate structure in series so as to have only to provide one contact to >=2 cells thereby decreasing the number of contacts. CONSTITUTION:A memory cell comprising a MOSFET having a floating gate and a control gate consists of a circuit 10 where 4 cell elements MC1-MC4 are connected in series. Through the constitution above, the drain of the element 1 is connected to a high voltage write voltage VP via an enhancement MOSFET 11 for write voltage application and the source of the element 4 is connected to the earth at 0V. A voltage Vdata in response to a write voltage is applied to the gate of the FET11 and selection voltages VG1-VG4 are applied to the control gate of the four elements MC1-MC4 respectively. Thus, one contact is enough to the series circuit 10 to reduce the area of the contact in case of large capacity manufacture.

Inventors

  • 👤 Hiroshi Iwahashi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 02:32
CPC Classifications
—

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS5771587U Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag