Memory tester APG with flexible Z register programming

Abstract

Abstract An algorithmic pattern generator (APG) in a memory tester having a programmable first ALU generating a first value on a first output data path; a programmable Z ALU generating a Z value on an Z output data path; and a programmable second ALU having terminals to receive the Z value from the Z ALU and a circuit to insert bits of the received Z value into low order bits of a second value before outputting the second value on a second output data path. In embodiments, the first value and the second value are generated to define a location in an array of memory cells of a memory under test; and the second value contains low order bits corresponding to address bits that are incremented internally by the memory under test in a burst mode of operation. Also, a method of programming a memory tester APG to test a memory device including providing to the APG for execution a single instruction setting a value representing a non-zero burst length n and a value representing a non-zero seed for generating interleaved addresses. In embodiments, the method includes providing an increment instruction to a counter n times for execution by the APG without an intervening instruction to reset the counter; and using the n values of the counter from the preceding step to form n addresses to test the memory device in a burst mode of operation with an interleaved addressing mode.

Inventors

• 👤 Michael J Sobelman

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