Circuit designing apparatus, circuit designing method and timing distribution apparatus

Claim 2

1 . A circuit designing apparatus, comprising: a circuit information database for storing information regarding a circuit; a designing processing section for reading out the information regarding the circuit from said circuit information database and designing the circuit for each predetermined unit to be processed; and a design information database for storing design information, obtained by said designing processing section, including at least peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit.

Claim 3

2 . The circuit designing apparatus as claimed in claim 1 , wherein said designing processing section includes: a peculiarizing processing section for reading out the peculiarizing information from said design information database and applying different names with each other to the individual units to be processed; a test circuit production processing section for reading out the change history information from said design information database and producing a test circuit of a higher hierarchical layer; and a load adjustment processing section for reading out the terminal load and driving capacity information from said design information database, applying the design information to terminals included in a circuit of the higher hierarchical layer and adjusting the load based on the design information.

Claim 4

3 . The circuit designing apparatus as claimed in claim 2 , wherein at least one of said peculiarizing processing section, test circuit production processing section and load adjustment processing section performs hierarchical design wherein the circuit is designed in a state wherein one of the units to be processed hierarchically contains another unit designed independently.

Claim 5

4 . The circuit designing apparatus as claimed in claim 3 , wherein said peculiarizing processing section includes: a peculiar name application rule setting section for setting a peculiar name application rule in accordance with which a peculiar name should be applied to each of the units to be processed based on a parameter regarding the names of the circuit elements based on said design information database; and a peculiar name production section for producing a peculiar name different from the peculiar names applied to the units which is processed already for any of the units to be processed based on the peculiar name application rule set by said peculiar name application rule setting section.

Claim 6

5 . The circuit designing apparatus as claimed in claim 4 , wherein said peculiarizing processing section further includes a plural-reference analysis section for searching for a location at which a plurality of same circuit units is used and discriminating a hierarchical layer, a cell and a black box regarding a type of the circuit units at the location, and said peculiar name production section produces a peculiar name for each of the plural-reference units and single-reference units discriminated by said plural-reference analysis section.

Claim 7

6 . The circuit designing apparatus as claimed in claim 5 , wherein said peculiarizing processing section further includes a circuit data duplication section for allocating peculiar names produced by said peculiar name production section to the plural-reference units and the single-reference units to duplicate the circuit data.

Claim 8

7 . The circuit designing apparatus as claimed in claim 3 , wherein at least one of said peculiarizing processing section, test circuit production processing section and load adjustment processing section includes: a processing object discrimination section for discriminating, when the higher hierarchical layer is to be processed, whether or not the unit to be processed is an object of processing based on the design information written in said design information database; and a processing data acquisition section for acquiring circuit data of the unit to be processed from said circuit information database based on a discrimination by said processing object discrimination section of whether or not the unit to be processed is an object processed.

Claim 9

8 . The circuit designing apparatus as claimed in claim 2 , wherein at least one of said peculiarizing processing section, test circuit production processing section and load adjustment processing section includes a processing object discrimination section for discriminating based on the design information written in said design information data base whether or not the unit to be processed is an object of the processing.

Claim 10

9 . The circuit designing apparatus as claimed in claim 2 , wherein said processing object discrimination section discriminates, based on first unit information regarding a processing result of a first unit obtained by processing the first unit of the design information, whether or not a unit included in a second unit to be processed next has been processed already.

Claim 11

10 . The circuit designing apparatus as claimed in claim 3 , wherein said test circuit production processing section includes a hierarchical layer matching restoration section for eliminating terminal mismatching between a terminal added for receiving a test signal input in a lower hierarchical layer and a terminal in the layer referred to by a higher hierarchical layer.

Claim 12

11 . The circuit designing apparatus as claimed in claim 2 , wherein at least one of said peculiarizing processing section, test circuit production processing section and load adjustment processing section performs engineering change order design where in some of the units to be processed is changed while the other units of the circuit are not changed to proceed with re-designing.

Claim 13

12 . The circuit designing apparatus as claimed in claim 11 , wherein at least one of said peculiarizing processing section, test circuit production processing section and load adjustment processing section includes a design information read-in section-for reading in normal design information produced upon normal design, and a processing object discrimination section for discriminating circuit data to be processed using the normal design information and engineering change order design object unit information given in the form of a parameter, and designs a circuit which is common to a circuit designed normally using the normal design information except a changed portion.

Claim 14

13 . The circuit designing apparatus as claimed in claim 11 , wherein said peculiarizing processing section includes, in order to duplicate, when the higher hierarchical layer refers to the design information, the unit to be processed by a number of times equal to the number of times by which the design information is referred to and apply a peculiar name to each of the units to be processed obtained by the duplication, a processing object discrimination section for discriminating based on the design information written in said design information database whether or not the unit to be processed is an object of processing, and a peculiar name production section for producing, when said processing object discrimination section discriminates that the unit to be processed is an object of processing, a peculiar name so as to establish a reference relationship same as the reference relationship stored in said design information database, but producing, when said processing object discrimination section discriminates that the unit to be processed is not an object of processing, a peculiar name different from the peculiar names allocated already.

Claim 15

14 . The circuit designing apparatus as claimed in claim 11 , wherein said test circuit production processing section includes a circuit analysis section for using the normal design information produced upon normal design with regard to an engineering change order design object unit and the test circuit rule based on said design information database to extract identification data for identification of a portion with regard to which a test circuit same as that upon the normal design can be produced and another portion with regard to which a new test circuit should be produced.

Claim 16

15 . The circuit designing apparatus as claimed in claim 11 , wherein said test circuit production processing section includes a hierarchical layer matching restoration section for eliminating terminal mismatching between a terminal added for receiving a test signal input in a lower hierarchical layer and a terminal in the layer referred to by a higher hierarchical layer, and said hierarchical layer matching restoration section uses the normal design information regarding normal design and the terminal information of the engineering chain order design object unit and the higher hierarchical layer from within the design information to restore the hierarchical layer matching.

Claim 17

16 . The circuit designing apparatus as claimed in claim 14 , wherein said test circuit production processing section further includes a test circuit production section for producing a test circuit which is the same in regard to a portion of the engineering change order design object unit with regard to which a test circuit same as that upon the normal design can be produced based on the identification data extracted by said circuit analysis section, but producing a test circuit conforming to the test circuit rule with regard to another portion of the engineering change order design object unit with regard to which a new test circuit should be produced.

Claim 18

17 . The circuit designing apparatus as claimed in claim 2 or 11 , wherein said peculiarizing processing section further includes a design information read-in section for reading out the design information from said design information database, and said design information read-in section makes the hierarchical layer names before the peculiarizing and the hierarchical layer names after the peculiarizing correspond to each other so as to allow the circuit data after the peculiarizing to be referred to with the hierarchical layer names before the peculiarizing.

Claim 19

18 . The circuit designing apparatus as claimed in claim 2 , wherein said load adjustment processing section includes: a load analysis section for analyzing a terminal capacity which can be driven by a logic element to extract an undrivable terminal or terminals; and a circuit adjustment section for adjusting the driving capacity of the undrivable terminal or terminals extracted by said load analysis section.

Claim 20

19 . The circuit designing apparatus as claimed in claim 1 , wherein said circuit information database includes: a circuit information writing section for writing circuit information for each processed unit into said circuit information database in at least one of hierarchical design and engineering change order design; and a reference section connected to said circuit information writing section for referring to the circuit information written for each unit to be processed.

Claim 21

20 . The circuit designing apparatus as claimed in claim 11 , wherein said design information database includes a plurality of storage sections for individually storing the circuit elements into individual files.

Claim 22

21 . A circuit designing method, comprising: a processing production step of producing, by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed, first unit information which relates to a processing result of a first unit obtained by processing the first unit; a design information collection step of collecting design information including at least peculiarizing information of circuit elements, the design information being produced in the processing production step, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit; a design information writing step of writing the design information collected in the design information collection step for each unit to be processed into a design information database connected to said design processing section for storing the design information; a reference step of referring to the design information regarding the first unit in order to process a second unit based on the design information written in the design information writing step; a recognition step of recognizing a reference relationship regarding the design information relating to the first unit referred-to in the reference step; a circuit information database reference step of referring to unit information regarding a position and a result of the processing stored in said circuit information database based on the reference relationship obtained in the reference step; and a circuit information database writing step of updating the circuit data obtained after a design processing.

Claim 23

21 . A circuit designing method, comprising: a processing production step of producing, by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed, first unit information which relates to a processing result of a first unit obtained by processing the first unit; a design information collection step of collecting design information including at least peculiarizing information of circuit elements, the design information being produced in the processing production step, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit; a design information writing step of writing the design information collected in the design information collection step for each unit to be processed into a design information database connected to said design processing section for storing the design information; a reference step of referring to the design information regarding the first unit in order to process a second unit based on the design information written in the design information writing step; a recognition step of recognizing a reference relationship regarding the design information relating to the first unit referred-to in the reference step; a circuit information database reference step of referring to unit information regarding a position and a result of the processing stored in said circuit information database based on the reference relationship obtained in the reference step; and a circuit information database writing step of updating the circuit data obtained after a design processing.

Claim 24

22 . A circuit designing method, comprising: a first processing step of processing a fourth unit which contains a third unit by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed; a third unit information collection step of collecting third unit information regarding a processing result of the third unit being produced in the first processing step; a design information writing step of writing the third unit information collected in the third unit information collection step into a design information database connected to said design processing section for storing the design information; and a discrimination step of discriminating, based on the third unit information written in the design information writing step, whether or not a third processed unit obtained by changing the third unit contains a fourth processed unit obtained by changing the fourth unit and discriminating whether or not the third processed unit is equivalent to the third unit.

Claim 25

22 . A circuit designing method, comprising: a first processing step of processing a fourth unit which contains a third unit by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed; a third unit information collection step of collecting third unit information regarding a processing result of the third unit being produced in the first processing step; a design information writing step of writing the third unit information collected in the third unit information collection step into a design information database connected to said design processing section for storing the design information; and a discrimination step of discriminating, based on the third unit information written in the design information writing step, whether or not a third processed unit obtained by changing the third unit contains a fourth processed unit obtained by changing the fourth unit and discriminating whether or not the third processed unit is equivalent to the third unit.

Claim 26

23 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to read out information regarding a circuit from a circuit information database in which the information regarding the circuit is stored and design the circuit for each predetermined unit to be processed and then store design information obtained by the design and including at least peculiarizing information of a circuit element, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit.

Claim 27

23 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to read out information regarding a circuit from a circuit information database in which the information regarding the circuit is stored and design the circuit for each predetermined unit to be processed and then store design information obtained by the design and including at least peculiarizing information of a circuit element, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit.

Claim 28

24 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to execute: a processing production step of producing, by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed, first unit information which relates to a processing result of a first unit obtained by processing the first unit; a design information collection step of collecting design information including at least peculiarizing information of circuit elements being produced in the processing production step, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit; a design information writing step of writing the design information collected in the design information collection step for each unit to be processed into a design information database connected to said design processing section for storing the design information; a reference step of referring to the design information regarding the first unit in order to process a second unit based on the design information written in the design information writing step; a recognition step of recognizing a reference relationship regarding the design information relating to the first unit referred to in the reference step; a circuit information database reference step of referring to unit information regarding a position and a result of the processing stored in said circuit information database based on the reference relationship obtained in the reference step; and a circuit information database writing step of updating the circuit data obtained in the design processing.

Claim 29

24 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to execute: a processing production step of producing, by means of a designing processing section for reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and designing the circuit for each predetermined unit to be processed, first unit information which relates to a processing result of a first unit obtained by processing the first unit; a design information collection step of collecting design information including at least peculiarizing information of circuit elements being produced in the processing production step, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit; a design information writing step of writing the design information collected in the design information collection step for each unit to be processed into a design information database connected to said design processing section for storing the design information; a reference step of referring to the design information regarding the first unit in order to process a second unit based on the design information written in the design information writing step; a recognition step of recognizing a reference relationship regarding the design information relating to the first unit referred to in the reference step; a circuit information database reference step of referring to unit information regarding a position and a result of the processing stored in said circuit information database based on the reference relationship obtained in the reference step; and a circuit information database writing step of updating the circuit data obtained in the design processing.

Claim 30

25 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to execute: a first processing step of reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and processing a fourth unit which contains a third unit by means of a designing processing section for designing the circuit for each predetermined unit to be processed; a third unit information collection step of collecting third unit information regarding a processing result of the third unit being produced in the first processing step; a design information writing step of writing the third unit information collected in the third unit information collection step into a design information database connected to said design processing section for storing the design information; and a discrimination step of discriminating, based on the third unit information written in the design information writing step, whether or not a third processed unit obtained by changing the third unit contains a fourth processed unit obtained by changing the fourth unit and discriminating whether or not the third processed unit is equivalent to the third unit.

Claim 31

25 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function so as to execute: a first processing step of reading out information regarding a circuit from a circuit information database which stores information regarding the circuit and processing a fourth unit which contains a third unit by means of a designing processing section for designing the circuit for each predetermined unit to be processed; a third unit information collection step of collecting third unit information regarding a processing result of the third unit being produced in the first processing step; a design information writing step of writing the third unit information collected in the third unit information collection step into a design information database connected to said design processing section for storing the design information; and a discrimination step of discriminating, based on the third unit information written in the design information writing step, whether or not a third processed unit obtained by changing the third unit contains a fourth processed unit obtained by changing the fourth unit and discriminating whether or not the third processed unit is equivalent to the third unit.

Claim 32

26 . A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers for receiving block information regarding a function of a circuit from a plurality of timing information databases having netlist information regarding a wiring line scheme and outputting timing distribution values obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the timing distribution values to and from said plurality of timing distribution production sections.

Claim 33

26 . A timing distribution apparatus for use for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers for receiving block information regarding a function of a circuit from a plurality of timing information databases having netlist information regarding a wiring line scheme and outputting timing distribution values obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the timing distribution values to and from said plurality of timing distribution production sections.

Claim 34

27 . The timing distribution apparatus as claimed in claim 26 , wherein said timing distribution production sections are formed as agents individually provided corresponding to the plurality of design hierarchical layers and having a hierarchical layer entity having design information and program data for processing the design information, and said inter-hierarchical layer association manager is formed as a manager connected to said timing distribution production sections as said agents for transmitting and receiving information regarding the timing distribution values individually to and from the plurality of design hierarchical layers.

Claim 35

28 . The timing distribution apparatus as claimed in claim 27 , wherein each of said timing distribution production sections includes: a logic/constraint information storage section for storing logic/constraint information having at least a netlist regarding a source code of a design language, the block information and constraint information regarding wiring line; a floor planning section connected to said logic/constraint information storage section for distributing timings based on a floor plan regarding arrangement of circuit elements and wiring lines between the circuit elements to perform provisional wiring line; a timing information storage section connected to said floor planning section for storing the netlist information; and a distribution manager connected to said logic/constraint information storage section and said timing information storage section for outputting the delay value based on at least the netlist information.

Claim 36

29 . The timing distribution apparatus as claimed in claim 28 , wherein said floor planning section includes: an arrangement processing section connected to said logic/constraint information storage section for presenting a portion with regard to which a distribution value as attribute information can be improved and modified based on a slack from the constraint information and storing arrangement information originating from the delay element information; an actual wiring and provisional wiring execution section connected to said arrangement processing section for performing association with actual wiring and provisional wiring, and outputting wiring information; a wiring information storage section connected to said actual wiring and provisional wiring execution section for storing the wiring information; a physical technology information storage section for storing physical technology information including at least delay values per unit length corresponding to wiring line layers and load capacities per unit length in order to output the timing information; and a conversion section connected to said wiring information storage section and said physical technology information storage section for converting the wiring information into a delay value based on the delay length and the load capacity and outputting the delay value.

Claim 37

30 . The timing distribution apparatus as claimed in claim 29 , wherein said actual wiring and provisional wiring execution section performs wiring using both of actual wiring which requires long calculation time and provisional wiring which requires short calculation time and extracts the timing distribution values.

Claim 38

31 . The timing distribution apparatus according to claim 29 , wherein said actual wiring and provisional wiring execution section includes: a Manhattan length provisional wiring section for performing Manhattan length provisional wiring for both of a printed circuit board and a large scale integrated circuit based on a result of arrangement of an arrangement supporting section which presents a portion with which the distribution value as attribute information can be improved and modified based on a slack from constraint information; an oblique Manhattan length provisional wiring section for performing provisional wiring using oblique wiring wherein a wiring line is located obliquely with respect to an edge of the printed circuit board based on the arrangement result; and an actual wiring association section for performing wiring for the printed circuit board and the large scale integrated circuit.

Claim 39

32 . The timing distribution apparatus as claimed in claim 31 , wherein said actual wiring and provisional wiring execution section performs the provisional wiring based on the Manhattan length provisional wiring, the oblique Manhattan length provisional wiring and the actual wiring.

Claim 40

33 . The timing distribution apparatus as claimed in claim 29 , wherein said actual wiring and provisional wiring execution section reads out the delay values and the load capacities of a selected hierarchical layer from said physical technology information storage section, varies the delay time per unit wiring line length and distributes the delay time.

Claim 41

34 . The timing distribution apparatus as claimed in claim 31 , wherein said actual wiring and provisional wiring execution section performs actual wiring based on a margin calculated with regard to the timing distribution value obtained by the provisional wiring and a wiring line congestion degree representative of the density of the wiring lines.

Claim 42

35 . The timing distribution apparatus as claimed in claim 31 , wherein said actual wiring and provisional wiring execution section outputs information for analysis regarding information which is insufficient in the actual wiring so as to allow cooperation with another designing apparatus which uses another computer which can perform only the actual wiring.

Claim 43

36 . The timing distribution apparatus as claimed in claim 31 , wherein said actual wiring and provisional wiring execution section performs the provisional wiring and the actual wiring based on at least a region in which wiring is inhibited and the wiring line congestion degree.

Claim 44

37 . The timing distribution apparatus as claimed in claim 31 , wherein said actual wiring and provisional wiring execution section discriminates based on a clock frequency used as a constraint condition whether or not arrival within time within which arrival is essentially required is possible and issues, if the arrival is impossible, an instruction to insert at least one of a buffer and a flip-flop into the netlist information between a plurality of circuit blocks.

Claim 45

38 . The timing distribution apparatus as claimed in claim 31 , wherein said actual wiring and provisional wiring execution section arranges terminals included in circuit blocks based on the constraint information.

Claim 46

39 . The timing distribution apparatus as claimed in claim 27 , wherein said inter-hierarchical layer association manager extracts a circuit block whose timing information data is insufficient and inputs the extracted circuit block to said timing information database, and notifies a designer of the circuit block whose timing information data is insufficient.

Claim 47

40 . The timing distribution apparatus as claimed in claim 28 , wherein said floor planning section can change a wiring line width in a circuit block while the actual wiring or the provisional wiring is proceeding.

Claim 48

41 . The timing distribution apparatus as claimed in claim 27 , wherein said inter-hierarchical layer association manager can change the combination of said plurality of distribution managers.

Claim 49

42 . The timing distribution apparatus as claimed in claim 28 , wherein each of said timing distribution production sections further includes a waveform analysis information production section for producing information for waveform analysis of a printed circuit board from input/output buffer information of a hierarchical layer of a large scale integration circuit.

Claim 50

43 . The timing distribution apparatus as claimed in claim 28 , wherein each of said timing distribution production sections outputs the timing distribution value based on another timing specification set in advance and the timing distributed by said floor planning section.

Claim 51

44 . The timing distribution apparatus as claimed in claim 28 , wherein said floor planning section can change at least one of a scale and a shape of the circuit blocks while the actual wiring or the provisional wiring is proceeding.

Claim 52

45 . The timing distribution apparatus as claimed in claim 28 , wherein each of said timing distribution production sections reads in timing distribution values back annotated from logical design or layout examination using the source code.

Claim 53

46 . The timing distribution apparatus as claimed in claim 28 , wherein each of said timing distribution production sections further includes an annotator for writing information arising from the timing distribution values into the source code.

Claim 54

47 . The timing distribution apparatus as claimed in claim 46 , wherein said annotator writes netlist information regarding a wiring scheme into the source code.

Claim 55

48 . The timing distribution apparatus as claimed in claim 29 , wherein said physical technology information storage section stores the wiring line length and the delay value per unit length and load capacity per unit length in a mutually associated relationship.

Claim 56

49 . The timing distribution apparatus as claimed in claim 26 , wherein said inter-hierarchical layer association manager receives a timing distribution specification changing request transmitted from one of said plurality of timing information databases, extracts any of the other timing information databases on which the timing distribution specification change may possibly have an influence, and inquires the pertaining timing information database for whether or not change of the timing distribution values is permissible.

Claim 57

50 . The timing distribution apparatus as claimed in claim 49 , wherein said inter-hierarchical layer association manager outputs, when a response representing that change of the timing distribution values is permissible is received from the pertaining timing information database, to the one timing information database a notification that change of the timing distribution values is permissible.

Claim 58

51 . The timing distribution apparatus as claimed in claim 50 , wherein said inter-hierarchical layer association manager updates, when the timing distribution values are changed, a higher hierarchical layer entity than the hierarchical layer in which the timing distribution values are changed.

Claim 59

52 . The timing distribution apparatus as claimed in claim 28 , wherein said distribution manager includes: a distribution editor connected to said logic/constraint information storage section for distributing timings; a database reference registration section connected to said distribution editor, said logic/constraint information storage section and said timing information storage section for outputting the netlist information; a self hierarchical layer timing information database outputting and other hierarchical layer timing information database reflection section for inputting and outputting timing distribution information of a hierarchical layer to which said distribution manager belongs and timing distribution information of the other hierarchical layer or layers; and an arbitration control section for performing arbitration.

Claim 60

53 . The timing distribution apparatus as claimed in claim 28 , wherein said distribution manager calculates a skew representative of a phase difference of an arrival time of a signal based on one or those of wiring line paths of netlist information regarding a wiring scheme which are other than a common wiring line path or paths.

Claim 61

54 . The timing distribution apparatus as claimed in claim 28 , wherein said distribution manager applies a name representative of a wiring line scheme as a sub signal name to each of the wiring line paths.

Claim 62

55 . The timing distribution apparatus as claimed in claim 28 , wherein said distribution manager applies a sub signal name in an associated relationship with a fan-out number.

Claim 63

56 . The timing distribution apparatus as claimed in claim 28 , wherein said distribution manager displays a gradation of a wired portion corresponding to the value of the constraint information in color on an operation screen.

Claim 64

57 . The timing distribution apparatus as claimed in claim 28 , wherein said distribution manager displays the timing distribution values and a range in value within which the timing can be distributed on a figure which shows the circuit blocks.

Claim 65

58 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function as: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers for receiving block information regarding functions of a circuit from a plurality of timing information databases having netlist information regarding a wiring line scheme and outputting timing distribution values obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager connected to said plurality of timing distribution production sections for transmitting and receiving modification information regarding the timing distribution values to and from said plurality of timing distribution production sections.

Claim 66

58 . A computer-readable recording medium on which a program is recorded, the program causing a computer to function as: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers for receiving block information regarding functions of a circuit from a plurality of timing information databases having netlist information regarding a wiring line scheme and outputting timing distribution values obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager connected to said plurality of timing distribution production sections for transmitting and receiving modification information regarding the timing distribution values to and from said plurality of timing distribution production sections.