US3104331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay pulse generator
Assignee: Unisys Corp
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Filing: 1961-04-26
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Granted: 1963-09-17
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Expires: 1981-04-26
Abstract
No abstract record available.
Inventors
- 👤 Robert L Zinke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:00
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
164 words
A DELAY PULSE GENERATOR FOR PRODUCING AN OUTPUT PULSE HAVING LEADING AND TRAILING EDGES WHICH MAY BE INDEPENDENTLY DELAYED RELATIVE TO THE OCCURRENCE OF A TRIGGER PULSE, SAID GENERATOR COMPRISING FIRST AND SECOND TRANSISTORS CONNECTED IN CASCADE, EACH TRANSISTOR INCLUDING A BASE, A COLLECTOR AND AN EMITTER, THE EMITTER OF SAID FIRST TRANSISTOR BEING COUPLED TO THE BASE OF SAID SECOND TRANSISTOR, MEANS FOR INITIALLY BIASING TO CUT OFF THE BASES OF BOTH SAID FIRST AND SECOND TRANSISTORS, SAID MEANS INCLUDING A FIRST DIODE CONNECTED BETWEEN THE BASE AND EMITTER OF SAID FIRST TRANSISTOR AND A SECOND DIODE CONNECTED BETWEEN THE BASE AND EMITTER OF SAID SECOND TRANSISTOR, A CAPACITOR HAVING TWO TERMINALS, ONE OF SAID TERMINALS BEING DIRECTLY COUPLED TO THE BASE OF SAID FIRST TRANSISTOR, AND MEANS FOR COUPLING THE OTHER OF SAID TERMINALS TO THE COLLECTOR OF SAID FIRST TRANSISTOR, THE BASE OF SAID FIRST TRANSISTOR RECEIVING SAID TRIGGER PULSE AND THE COLLECTOR OF SAID SECOND TRANSISTOR DELIVERING SAID OUTPUT PULSE.
Claim 2
Dependent Claim
164 words
A DELAY PULSE GENERATOR FOR PRODUCING AN OUTPUT PULSE HAVING LEADING AND TRAILING EDGES WHICH MAY BE INDEPENDENTLY DELAYED RELATIVE TO THE OCCURRENCE OF A TRIGGER PULSE, SAID GENERATOR COMPRISING FIRST AND SECOND TRANSISTORS CONNECTED IN CASCADE, EACH TRANSISTOR INCLUDING A BASE, A COLLECTOR AND AN EMITTER, THE EMITTER OF SAID FIRST TRANSISTOR BEING COUPLED TO THE BASE OF SAID SECOND TRANSISTOR, MEANS FOR INITIALLY BIASING TO CUT OFF THE BASES OF BOTH SAID FIRST AND SECOND TRANSISTORS, SAID MEANS INCLUDING A FIRST DIODE CONNECTED BETWEEN THE BASE AND EMITTER OF SAID FIRST TRANSISTOR AND A SECOND DIODE CONNECTED BETWEEN THE BASE AND EMITTER OF SAID SECOND TRANSISTOR, A CAPACITOR HAVING TWO TERMINALS, ONE OF SAID TERMINALS BEING DIRECTLY COUPLED TO THE BASE OF SAID FIRST TRANSISTOR, AND MEANS FOR COUPLING THE OTHER OF SAID TERMINALS TO THE COLLECTOR OF SAID FIRST TRANSISTOR, THE BASE OF SAID FIRST TRANSISTOR RECEIVING SAID TRIGGER PULSE AND THE COLLECTOR OF SAID SECOND TRANSISTOR DELIVERING SAID OUTPUT PULSE.
References Cited (Backward Citations)
US2872571A
Cited
US3018420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1966-09-16 | 1967-03-18 | 1967-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1970-09-16 | 1971-03-18 | 1971-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1974-09-16 | 1975-03-18 | 1975-09-17 | $7700.00 | Window Closed / Lapsed |