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US3108197A Expired / Lapsed US ⏱️ 0.0 years remaining

Feedback control logarithmic amplifier

Assignee: Individual
•
Filing: 1961-02-16
•
Granted: 1963-10-22
•
Expires: 1981-02-16
📄 Original PDF 🌐 Google Patents

Abstract

No abstract record available.

Inventors

  • 👤 William S Levin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 23:29
CPC Classifications
H; H03; H03G; H03G7/00; H03G7/001

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 123 words
A FEEDBACK CONTROLLED LOGARITHMIC AMPLIFIER STAGE COMPRISING: A TRANSISTOR AMPLIFIER CIRCUIT INCLUDING FIRST AND SECOND TRANSISTORS, EACH HAVING EMITTER, COLLECTOR, AND BASE ELECTRODE, SAID FIRST TRANSISTOR BEING COLLECTOR-TO-BASE COUPLED TO SAID SECOND TRANSISTOR, THE EMITTER OF THE FIRST TRANSISTOR BEING COUPLED TO AN INPUT TERMINAL AND THE EMITTER OF THE SECOND TRANSISTOR BEING COUPLED TO AN OUTPUT TERMINAL, THE COLLECTOR-TO-BASE COUPLING AND THE BASE OF THE FIRST TRANSITOR BEING COUPLED IN A VOLTAGE DIVIDER CIRCUIT AND THE COLLECTOR OF SAID SECOND TRANSISTOR BEING COUPLED TO FIXED ZERO POTENTIAL; A NEGATIVE FEEDBACK CIRCUIT COUPLING THE OUTPUT TERMINAL OF THE SECOND TRANSISTOR TO THE BASE OF SAID FIRST TRANSISTOR, SAID FEEDBACK CIRCUIT INCLUDING A PLURALITY OF DIODES IN PARALLEL AND EACH BIASED AT A DIFFERENT
Claim 2
Dependent Claim 123 words
A FEEDBACK CONTROLLED LOGARITHMIC AMPLIFIER STAGE COMPRISING: A TRANSISTOR AMPLIFIER CIRCUIT INCLUDING FIRST AND SECOND TRANSISTORS, EACH HAVING EMITTER, COLLECTOR, AND BASE ELECTRODE, SAID FIRST TRANSISTOR BEING COLLECTOR-TO-BASE COUPLED TO SAID SECOND TRANSISTOR, THE EMITTER OF THE FIRST TRANSISTOR BEING COUPLED TO AN INPUT TERMINAL AND THE EMITTER OF THE SECOND TRANSISTOR BEING COUPLED TO AN OUTPUT TERMINAL, THE COLLECTOR-TO-BASE COUPLING AND THE BASE OF THE FIRST TRANSITOR BEING COUPLED IN A VOLTAGE DIVIDER CIRCUIT AND THE COLLECTOR OF SAID SECOND TRANSISTOR BEING COUPLED TO FIXED ZERO POTENTIAL; A NEGATIVE FEEDBACK CIRCUIT COUPLING THE OUTPUT TERMINAL OF THE SECOND TRANSISTOR TO THE BASE OF SAID FIRST TRANSISTOR, SAID FEEDBACK CIRCUIT INCLUDING A PLURALITY OF DIODES IN PARALLEL AND EACH BIASED AT A DIFFERENT

References Cited (Backward Citations)

US2760008A Cited
US2774825A Cited
US2863955A Cited
US2802118A Cited
DE1094807B Cited
US2906933A Cited
US2912654A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1966-10-21 1967-04-22 1967-10-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1970-10-21 1971-04-22 1971-10-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1974-10-21 1975-04-22 1975-10-22 $7700.00 Window Closed / Lapsed

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