Dynamic storage circuit utilizing two tunnel diodes and reflective delay line

Claim 1

A DYNAMIC STORAGE CIRCUIT COMPRISING, IN COMBINATION, A REFLECTIVE DELAY LINE, A MEMORY ELEMENT CONNECTED TO SAID DELAY LINE, SAID MEMORY ELEMENT COMPRISING TWO NEGATIVE RESISTANCE ELEMENTS CONNECTED IN SERIES IN THE SAME POLARITY, SAID NEGATIVE RESISTANCE ELEMENTS HAVING SUBSTANTIALLY THE SAME CHARACTERISTICS AND IN WHICH CURRENT FLOWING THEREIN IN OPERATION IS A MULTIVALUE FUNCTION OF VOLTAGE APPLIED THERETO, MEANS FOR DEVELOPING A VOLTAGE OF OPPOSITE POLARITIES INTERMEDIATE SAID NEGATIVE RESISTANCE ELEMENTS IN WHICH THE VOLTAGE POLARITY IS REPRESENTATIVE OF BINARY CONDITIONS "O" AND "I" COMPRISING, MEANS COMPRISING CONNECTIONS FOR SIMULTANEOUSLY APPLYING POSITIVE PULSES AND THE OTHER COMPRISING NEGATIVE PULSES IN PHASE WITH SAID POSITIVE PULSES, THE LAST-MENTIONED MEANS COMPRISING CONNECTIONS FOR APPLYING ONE OF SAID CLOCK VOLTAGES TO ONE NEGATIVE RESISTANCE ELEMENT AND CONNECTIONS FOR APPLYING THE OTHER CLOCK VOLTAGE TO THE OTHER NEGATIVE RESISTANCE ELEMENT, AND MEANS CONNECTED INTERMEDIATE SAID NEGATIVE RESISTANCE ELEMENTS COUPLING SAID MEMORY ELEMENTS TO SAID DELAY LINE AT AN END OTHER THAN THE REFLECTIVE END THEREOF, WHEREBY SAID VOLTAGE DEVELOPED INTERMEDIATE SAID NEGATIVE RESISTANCE ELEMENTS IS APPLIED TO SAID DELAY LINE AND IS REFLECTED BACK TO SAID MEMORY ELEMENT AND IS AMPLIFIED AND REPRODUCED AT EACH CLOCK PERIOD DETERMINED BY SAID CLOCK VOLTAGES.