Bidirectional memory and gate synchronzing circuit for a variable frequency oscillator

Claim 1

A SAMPLER CIRCUIT FOR STORING THE VALUE AT PARTICULAR INTERVALS OF AN INPUT SIGNAL VARYING WITH TIME AND SHIFTABLE IN OPPOSITE SENSES FROM A DATUM POTENTIAL, COMPRISING AN NPN TRANSISTOR, A PNP TRANSISTOR, EACH TRANSISTOR HAVING COLLECTOR, BASE AND EMITTER ELECTRODES, MEANS CONNECTING BOTH COLLECTOR ELECTRODES TOGETHER AND TO AN INPUT TERMINAL TO RECEIVE SAID SIGNAL VARYING WITH TIME, MEANS CONNECTING SAID EMITTERS TO A COMMON JUNCTION, A CAPACITOR AND A PARALLEL RESISTOR CONNECTED IN PARALLEL BETWEEN SAID COMMON JUNCTION AND A TERMINAL MAINTAINED AT SAID DATUM POTENTIAL, MEANS SUPPLYING TO THE BASE ELECTRODES OF THE RESPECTIVE TRANSISTORS BIASING POTENTIALS TENDING TO HOLD SAID TRANSISTORS IN A RELATIVELY NON-CONDUCTIVE CONDITION, AND MEANS EFFECTIVE DURING SAID PARTICULAR INTERVALS TO SUPPLY TO SAID BASE ELECTRODES DATA PULSE POTENTIALS EFFECTIVE TO OVERCOME SAID BIASING POTENTIALS, SAID DATA PULSE POTENTIALS VARYING IN OPPOSITE SENSES AND BEING EFFECTIVE TO RENDER ONE OR THE OTHER OF SAID TRANSISTORS SUBSTANTIALLY CONDUCTIVE, DEPENDING UPON THE SENSE OF THE DEPARTURE OF SAID INPUT SIGNAL FROM SAID DATUM POTENTIAL, AND THEREBY TO CHARGE SAID CAPACITOR TO A POTENTIAL SERVING AS A MEASURE OF THE SIGNAL POTENTIAL DURING SAID INTERVAL, AND AN OUTPUT TERMINAL CONNECTED TO SAID COMMON JUNCTION.