US3181004A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary memory device employing flipflop that is controlled by in-phase drivers
Assignee: Individual
•
Filing: 1961-08-03
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Granted: 1965-04-27
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Expires: 1981-08-03
Abstract
No abstract record available.
Inventors
- 👤 Guckel Henry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:09
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/012
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
164 words
A BINARY MEMORY ELEMENT COMPRISING: (A) AN INFORMATION STORAGE CIRCUIT COMPRISING: (1) FIRST AND SECOND TRANSISTORS, EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, (2) A FEEDBACK RESISTOR CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE BASE OF SAID SECOND TRANSISTOR, (3) AN INPUT TERMINAL CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR FOR RECEIVING BINARY INPUT SIGNALS, (4) AN OUTPUT CIRCUIT CONNECTED TO THE COLLECTOR OF SAID SECOND TRANSISTOR, (5) A SOURCE OF ENERGIZING POTENTIAL HAVING A PLURALITY OF TAPS THEREON, AND (6) RESISTANCE MEANS CONNECTING EACH OF SAID EMITTERS TO SAID SOURCE OF POTENTIAL; (B) FIRST AND SECOND DIODES PROVIDED WITH ANODE AND CATHODE ELECTRODES, THE CATHODE OF SAID FIRST DIODE BEING CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR, AND THE ANODE OF SAID SECOND DIODE BEING CONNECTED TO THE BASE OF SAID SECOND TRANSISTOR; (C) FIRST ND SECOND BIASING CIRCUIT MEANS CONNECTED TO RESPECTIVE BASES FOR ESTABLISHING THE POTENTIALS AT ONE ELECTRODE OF EACH OF SAID DIODES AND INCLUDING
Claim 2
Dependent Claim
164 words
A BINARY MEMORY ELEMENT COMPRISING: (A) AN INFORMATION STORAGE CIRCUIT COMPRISING: (1) FIRST AND SECOND TRANSISTORS, EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, (2) A FEEDBACK RESISTOR CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE BASE OF SAID SECOND TRANSISTOR, (3) AN INPUT TERMINAL CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR FOR RECEIVING BINARY INPUT SIGNALS, (4) AN OUTPUT CIRCUIT CONNECTED TO THE COLLECTOR OF SAID SECOND TRANSISTOR, (5) A SOURCE OF ENERGIZING POTENTIAL HAVING A PLURALITY OF TAPS THEREON, AND (6) RESISTANCE MEANS CONNECTING EACH OF SAID EMITTERS TO SAID SOURCE OF POTENTIAL; (B) FIRST AND SECOND DIODES PROVIDED WITH ANODE AND CATHODE ELECTRODES, THE CATHODE OF SAID FIRST DIODE BEING CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR, AND THE ANODE OF SAID SECOND DIODE BEING CONNECTED TO THE BASE OF SAID SECOND TRANSISTOR; (C) FIRST ND SECOND BIASING CIRCUIT MEANS CONNECTED TO RESPECTIVE BASES FOR ESTABLISHING THE POTENTIALS AT ONE ELECTRODE OF EACH OF SAID DIODES AND INCLUDING
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-04-26 | 1968-10-26 | 1969-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-04-26 | 1972-10-26 | 1973-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-04-26 | 1976-10-26 | 1977-04-27 | $7700.00 | Window Closed / Lapsed |