Multiple accumulators

Claim 1

IN A DATA ACCUMULATING SYSTEM HAVING A PLURALITY OF ACCUMULATING REGISTERS IMPLEMENTED WITH A CYCLIC MEMORY DEVICE HAVING A PLURALITY OF TEMPORAL SECTORS SEQUENTIALLY AVAILABLE, EACH SECTOR HAVING A PLURALITY OF BINARY CELLS FOR STORING A FOUR-BIT, BINARY-CODED DECIMAL AUGEND, THE COMBINATION COMPRISING: A SOURCE OF FOUR-BIT, BINARY-CODED DECIMAL ADDENDS; A FIRST BINARY ADDER; A FIRST MEANS FOR TRANSLATING AN AUGEND FROM A GIVEN ACCUMULATOR REGISTER TO SAID FIRST BINARY ADDER; A SOURCE OF MARKER PULSES SYNCHRONIZED WITH SAID ACCUMULATOR REGISTERS; A SECOND MEANS RESPONSIVE TO A GIVEN MARKER PULSE FOR TRANSLATING A GIVEN ADDEND DIGIT TO SAID FIRST BINARY ADDER; A THIRD MEANS COUPLED TO SAID FIRST BINARY ADDER FOR TRANSLATING A DECIMAL CARRY TO SAID FIRST ADDER FOR ADDITION TO THE AUGEND DIGIT OF HIGHER DECIMAL ORDER AS SAID GIVEN AUGEND IS TRANSLATED THERETO, SAID DECIMAL CARRY BEING PROPAGATED FOR TRANSLATION TO SAID FIRST BINARY ADDER WHEN THE BINARY ADDITION OF SAID GIVEN ADDEND DIGIT WITH AN AUGEND DIGIT IS GREATER THAN FIFTEEN; A SECOND BINARY ADDER; A REGISTER COUPLED TO SAID FIRST AND SECOND ADDERS FOR TRANSLATING A PRELIMINARY SUM FROM SAID FIRST BINARY ADDER TO SAID SECOND BINARY ADDER; A FOURTH MEANS COUPLED TO SAID REGISTER FOR DETECTING THE PRELIMINARY SUM OF A GIVEN ADDEND DIGIT TO AN AUGEND DIGIT GREATER THAN NINE, BUT LESS THAN SIXTEEN, AND FOR PROPAGATING IN RESPONSE THERETO A DECIMAL CARRY TO SAID FIRST BINARY ADDER FOR ADDITION TO THE AUGEND DIGIT OF HIGHER DECIMAL ORDER AS SAID GIVEN AUGEND IS TRANSLATED THERETO; A FIFTH MEANS RESPONSIVE TO A DECIMAL CARRY TRANSLATED BY SAID THIRD MEANS AND TO A DECIMAL CARRY PROPAGATED BY SAID FOURTH MEANS FOR ADDING A BINARY-CODED DECIMAL SIX TO SAID PRELIMINARY SUM IN SAID SECOND BINARY ADDER TO PRODUCE A FINAL SUM; MEANS CONNECTED TO SAID SECOND BINARY ADDER FOR INHIBITING THE PROPAGATION OF ANY DECIMAL CARRIES THEREFROM; AND MEANS FOR STORING SAID FINAL SUM IN SAID GIVEN ACCUMULATOR REGISTER.