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US3233120A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor trigger-pulse circuit

Assignee: Associated Electrical Industries Ltd
•
Filing: 1962-03-14
•
Granted: 1966-02-01
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Expires: 1982-03-14
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Abstract

No abstract record available.

Inventors

  • 👤 Darke James Anthony

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:16
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/145; H02M7/155; H02M7/1555; H02M7/15; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/72; H03K3/00; H03K3/02; H03K3/26; H03K3/30

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 264 words
AN ELECTRONIC FIRING CIRCUIT SUITABLE FOR TRIGGERING A CONTROLLED RECTIFIER AND COMPRISING: (A) A TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR; (B) AN ALTERNATING CURRENT SUPPLY HAVING A MAIN FREQUENCY IN THE ORDER OF 60 CYCLES PER SECOND; (C) A FIRST CIRCUIT FED BY THE ALTENATING CURRENT SUPPLY AND PRODUCING AS OUTPUT HALF-WAVE-RECTIFIED AND CLIPPED DIRECT VOLTAGE; (D) A SECOND CIRCUIT FED BY THE ALTERNATING CURRENT SUPPLY AND GENERATING A FLUCTUATING DIRECT VOLTAGE OF RAMP WAVEFORM AT THE SUPPLY FREQUENCY; (E) A THIRD CIRCUIT PRODUCING A CONTROLLABLE DIRECT CURRENT BIAS VOLTAGE DURING SUBSTANTIALLY THE WHOLE PERIOD OF EACH ALTERNATE HALF CYCLE OF THE ALTERNATING CURRENT SUPPLY; (F) A CIRCUIT FED BY SAID SECOND AND THIRD CIRCUITS AND CONNECTED BETWEEN SAID BASE AND EMITTER BY WHICH THE RAMP WAVEFORM AND THE CONTROLLABLE DIRECT CURRENT BIAS VOLTAGE ARE JOINTLY APPLIED BETWEEN THE BASE AND THE EMITTER TO RENDER THE TRANSISTOR CONDUCTIVE WHEN THE VOLTAGE OF THE RAMP WAVEFORM OVER-RIDES THE BIAS VOLTAGE; (G) ADJUSTABLE CIRCUIT MEANS FOR VARYING THE CONTROLLABLE DIRECT CURRENT BIAS VOLTAGE SO AS TO VARY THE POINT IN EACH OF THE SAID ALTERNATE HALF CYCLES AT WHICH THE TRANSISTOR WILL BECOME CONDUCTIVE; (H) AND AN ELECTRICAL NETWORK INCLUDING THE EMITTER AND THE COLLECTOR OF THE TRANSISTOR AND FORMING A BLOCKING-OSCILLATOR, SAID NETWORK BEING FED WITH THE HALF-WAVE-RECTIFIED AND CLIPPED VOLTAGE OUTPUT OF SAID FIRST CIRCUIT AND PRODUCING A TRAIN OF OUTPUT PULSES IN AN OUTPUT CIRCUIT DURING THE PART OF EACH OF THE SAID ALTERNATE HALF CYCLES WHEN THE TRANSISTOR IS CONDUCTIVE, THE PULSE REPETITION FREQUENCY BEING SEVERAL KILOCYCLES PER SECOND.
Claim 2
Dependent Claim 264 words
AN ELECTRONIC FIRING CIRCUIT SUITABLE FOR TRIGGERING A CONTROLLED RECTIFIER AND COMPRISING: (A) A TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR; (B) AN ALTERNATING CURRENT SUPPLY HAVING A MAIN FREQUENCY IN THE ORDER OF 60 CYCLES PER SECOND; (C) A FIRST CIRCUIT FED BY THE ALTENATING CURRENT SUPPLY AND PRODUCING AS OUTPUT HALF-WAVE-RECTIFIED AND CLIPPED DIRECT VOLTAGE; (D) A SECOND CIRCUIT FED BY THE ALTERNATING CURRENT SUPPLY AND GENERATING A FLUCTUATING DIRECT VOLTAGE OF RAMP WAVEFORM AT THE SUPPLY FREQUENCY; (E) A THIRD CIRCUIT PRODUCING A CONTROLLABLE DIRECT CURRENT BIAS VOLTAGE DURING SUBSTANTIALLY THE WHOLE PERIOD OF EACH ALTERNATE HALF CYCLE OF THE ALTERNATING CURRENT SUPPLY; (F) A CIRCUIT FED BY SAID SECOND AND THIRD CIRCUITS AND CONNECTED BETWEEN SAID BASE AND EMITTER BY WHICH THE RAMP WAVEFORM AND THE CONTROLLABLE DIRECT CURRENT BIAS VOLTAGE ARE JOINTLY APPLIED BETWEEN THE BASE AND THE EMITTER TO RENDER THE TRANSISTOR CONDUCTIVE WHEN THE VOLTAGE OF THE RAMP WAVEFORM OVER-RIDES THE BIAS VOLTAGE; (G) ADJUSTABLE CIRCUIT MEANS FOR VARYING THE CONTROLLABLE DIRECT CURRENT BIAS VOLTAGE SO AS TO VARY THE POINT IN EACH OF THE SAID ALTERNATE HALF CYCLES AT WHICH THE TRANSISTOR WILL BECOME CONDUCTIVE; (H) AND AN ELECTRICAL NETWORK INCLUDING THE EMITTER AND THE COLLECTOR OF THE TRANSISTOR AND FORMING A BLOCKING-OSCILLATOR, SAID NETWORK BEING FED WITH THE HALF-WAVE-RECTIFIED AND CLIPPED VOLTAGE OUTPUT OF SAID FIRST CIRCUIT AND PRODUCING A TRAIN OF OUTPUT PULSES IN AN OUTPUT CIRCUIT DURING THE PART OF EACH OF THE SAID ALTERNATE HALF CYCLES WHEN THE TRANSISTOR IS CONDUCTIVE, THE PULSE REPETITION FREQUENCY BEING SEVERAL KILOCYCLES PER SECOND.

References Cited (Backward Citations)

US2743907A Cited
US2774919A Cited
US3002110A Cited
US3056930A Cited
US3033996A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1969-01-31 1969-08-02 1970-02-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1973-01-31 1973-08-02 1974-02-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1977-01-31 1977-08-02 1978-02-01 $7700.00 Window Closed / Lapsed

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