US3235718A
Expired / Lapsed
US
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Magnetic device for performing complex logic functions
Assignee: Unisys Corp
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Filing: 1962-10-25
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Granted: 1966-02-15
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Expires: 1982-10-25
Abstract
No abstract record available.
Inventors
- 👤 Eugene Thomas Walendziewicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/383
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
516 words
+ ... +KI-1 COMPRISING: FIRST AND SECOND LOGICAL DATA REGISTERS, EACH OF SAID DATA REGISTERS COMPRISING A PLURALITY OF STAGES, ONE FOR EACH ORDER OF SIGNIFICANCE IN THE BINARY NUMBERS TO BE ADDED, SAID FIRST DATA REGISTER GENERATING R1 BITS OF BINARY INFORMATION WHICH ARE THE INVERSE OF THE RI FACTORS APPEARING IN THE DECODER TERMS OF SAID EQUATIONS AND REPRESENT THE INVERSE EXCLUSIVE-OR OF CORRESPONDING BITS OF INFORMATION APPEARING RESPECTIVELY ON TWO INPUT CHANNELS, SAID SECOND DATE REGISTER GENERATING KI BITS OF BINARY INFORMATION WHICH ARE THE INVERSE OF THE KI FACTORS APPEARING IN THE DECODER TERMS OF SAID EQUATIONS AND REPRESENT THE INVERSE AND FUNCTION OF CORRESPONDING BITS OF INFORMATION APPEARING RESPECTIVELY ON SAID INPUT CHANNELS, FIRST AND SECOND LOGICAL MATRIX REGISTERS, SAID FIRST MATRIX REGISTER GENERATING THE SIMULTANEOUSCARRY TERMS FOR THE ADDITION PROCESS IN ACCORDANCE WITH SAID SET OF EQUATIONS FOR SUCH TERMS, SAID FIRST MATRIX REGISTER COMPRISING, A FIRST PLURALITY OF MAGNETIC ELEMENTS EACH HAVING A SUBSTANTIALLY RECTANGULAR HYSTERESIS LOOP CHARACTERISTIC AND BEING CAPABLE OF ASSUMING OPPOSED STATES OF MAGNETIC FLUX REMANENCE, EACH SAID MAGNETIC ELEMENT REPRESENTING A SINGLE DECODER TERM OF SAID EQUATIONS, SAID SECOND MATRIX REGISTER ACCEPTING AND BUFFERING THE INFORMATION STORED IN SAID FIRST DATA REGISTER AND COMPRISING A SECOND PLURALITY OF MAGNETIC ELEMENTS EQUAL IN NUMBER AND CORRESPONDING TO THE STAGES OF SAID FIRST DATA REGISTER, INHIBIT LINES REPRESENTATIVE OF THE INVERSE OF THE INPUT VARIABLES APPEARING AS THE FACTORS OF THE DECODER TERMS OF SAID SIMULTANEOUS-CARRY EQUATIONS, SAID INHIBIT LINES CORRESPONDING TO THE FACTORS OF ANY GIVEN DECODER TERM AND BEING INDUCTIVELY COUPLED TO THE ELEMENT OF SAID FIRST PLURALITY OF MAGNETIC ELEMENTS REPRESENTING SAID GIVEN TERM, THOSE INHIBIT LINES CORRESPONDING ALSO TO THE INVERSE INPUT VARIABLES GENERATED BY SAID FIRST DATA REGISTER BEING INDUCTIVELY COUPLED AS WELL TO RESPECTIVE ONES OF SAID SECOND PLURALITY OF MAGNETIC ELEMENTS, SAID INHIBIT LINES BEING ADAPTED TO BE PULSED FROM A SOURCE OF CURRENT IN ACCORDANCE WITH THE BINARY INFORMATION STORED IN BOTH SAID FIRST AND SECOND DATA REGISTERS, A PLURALITY OF CONTROL LINES COUPLED TO SAID FIRST AND SECOND PLURALITIES OF MAGNETIC ELEMENTS, SAID CONTROL LINES BEING ADAPTED TO BE PULSED SELECTIVELY FROM A SOURCE OF CURRENT WHEREBY SELECTED MAGNETIC ELEMENTS TEND TO BE SWITCHED FROM ONE STATE OF REMANENCE TO THE OPPOSITE STATE OF REMANENCE, A FIRST PLURALITY OF SENSE LINES REPRESENTATIVE RESPECTIVELY OF SAID MATHEMATICAL EQUATIONS, EACH SAID SENSE LINE BEING INDUCTIVELY COUPLED IN COMMON TO ALL OF THE MAGNETIC ELEMENTS IN SAID FIRST MATRIX REGISTER WHICH REPRESENT DECODER TERMS IN A GIVEN ONE OF SAID EQUATIONS, A SECOND PLURALITY OF SENSE LINES INDUCTIVELY COUPLED RESPECTIVELY TO SAID SECOND PLURALITY OF MAGNETIC ELEMENTS, THE SWITCHING OF THE MAGNETIC ELEMENTS OF SAID FIRST AND SECOND MATRIX REGISTERS CAUSING OUTPUT VOLTAGES TO BE INDUCED IN THE SENSE LINES COUPLED TO SAID MAGNETIC ELEMENTS, THE OUTPUT VOLTAGES INDUCED RESPECTIVELY ON THE SENSE LINES ASSOCIATED WITH SAID FIRST AND SECOND MATRIX REGISTERS APPEARING AS BITS OF INFORMATION ON SAID TWO INPUT CHANNELS, AND MEANS FOR APPLYING SAID BITS OF CARRY INFORMATION IN COMMON TO BOTH SAID FIRST AND SECOND DATA REGISTERS.
Claim 2
Independent Claim
21 words
A SYSTEM FOR PERFORMING A FULLY PARALLEL BINARY ADDITION WHEREIN THE SIMULTANEOUS-CARRY INFORMATION IS DERIVED FROM EQUATIONS OF THE GENERAL FORM:
Claim 3
Dependent Claim
199 words
THE SYSTEM AS DEFINED IN CLAIM 1 WHEREIN SAID PLURALITY OF CONTROL LINES COMPRISES: A SEPARATE SET LINE INDUCTIVELY COUPLED RESPECTIVELY TO SAID FIRST AND SECOND PLURALITIES OF MAGNETIC ELEMENTS, SAID SET LINES BEING ADAPTED TO BE PULSED SELECTIVELY AT A PREDETERMINED TIME FROM A SOURCE OF CURRENT WHEREBY THE MAGNETIC ELEMENTS COUPLED THERETO TEND TO BE SWITCHED TOWARD THE FIRST OF SAID STATES OF MAGNETIC REMANENCE, A RESET LINE INDUCTIVELY COUPLED TO ALL SAID MAGNETIC ELEMENTS, SAID RESET LINE BEING ADAPTED TO BE PULSED FROM A SOURCE OF CURRENT WHEREBY ALL SAID MAGNETIC ELEMENTS TEND TO BE DRIVEN TOWARD THE SECOND OF SAID STATES OF MAGNETIC REMANENCE, MEANS FOR ENERGIZING CONCURRENTLY AT SAID PREDETERMINED TIME A SELECTED SET LINE AND CERTAIN INHIBIT LINES AS DETERMINED BY THE INFORMATION STORED IN SAID DATA REGISTERS, THE FLOW OF CURRENT THROUGH SAID LAST INHIBIT LINES PREVENTING THE SWITCHING OF THE MAGNETIC ELEMENTS COUPLED THERETO, THE ABSENCE OF SAID CURRENT FLOW IN THE NON-ENERGIZED INHIBIT LINES AT SAID PREDETERMINED TIME ALLOWING THE MAGNETIC ELEMENTS TO WHICH ARE NON-ENERGIZED LINES ARE COUPLED TO BE SWITCHED TOWARD SAID FIRST STATE IN RESPONSE TO CURRENT FLOW THROUGH THE SET LINES COUPLED TO SAID LAST ELEMENTS.
Claim 4
Dependent Claim
256 words
THE SYSTEM AS DEFINED IN CLAIM 1 FURTHER ADAPTED TO PERFORM A BINARY MULTIPLICATION BY THE PROCESS OF ITERATIVE ADDITION COMPRISING: A THIRD AND A FOURTH LOGICAL DATA REGISTER, SAID THIRD DATA REGISTER STORING THE BITS OF BINARY INFORMATION REPRESENTING THE MULTIPLICAND AND BEING CAPABLE OF RESTORING SAID INFORMATION AFTER EACH READOUT OF THE MULTIPLICAND, SAID FOURTH DATA REGISTER STORING THE BITS OF BINARY INFORMATION REPRESENTING THE MULTIPLIER AND BEING CAPABLE OF RESTORING AND SHIFTING SAID INFORMATION ONE BIT POSITION TO THE RIGHT AFTER EACH READ-OUT OF THE MULTIPLIER, A THIRD AND A FOURTH LOGICAL MATRIX REGISTER, MEANS FOR READING OUT THE INFORMATION STORED IN BOTH SAID THIRD AND FOURTH DATA REGISTERS AND APPLYING SUCH INFORMATION CONCURRENTLY TO SAID THIRD MATRIX REGISTER, SAID THIRD MATRIX REGISTER PERFORMING A LOGICAL PRODUCT OF THE LEAST SIGNIFICANT BIT REMAINING OF THE MULTIPLIER INFORMATION FROM SAID FOURTH DATA REGISTER WITH ALL THE BITS OF THE MULTIPLICAND INFORMATION FROM SAID THIRD DATA REGISTER, SAID THIRD MATRIX REGISTER THEREBY STORING SAID CONDITIONED MULTIPLICAND, MEANS FOR READING OUT THE PARTIAL PRODUCT SUM INFORMATION STORED IN SAID FIRST DATA REGISTER AND APPLYING SUCH INFORMATION TO SAID FOURTH MATRIX REGISTER, SAID FOURTH MATRIX REGISTER ACCEPTING AND BUFFERING SUCH INFORMATION AND PROVIDING A SHIFT TO THE RIGHT OF ONE BIT POSTION, SAID FOURTH MATRIX REGISTER THEREBY STORING SAID SHIFTED PARTIAL PRODUCT SUM, MEANS FOR TRANSFERRING THE BITS OF SAID PARTIAL PRODUCT SUM AND SAID CONDITIONED MULTIPLICAND FROM SAID THIRD AND FOURTH MATRIX REGISTERS RESPECTIVELY TO THE CORRESPONDING STAGES OF BOTH SAID FIRST AND SECOND DATA REGISTERS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-02-14 | 1969-08-16 | 1970-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-02-14 | 1973-08-16 | 1974-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-02-14 | 1977-08-16 | 1978-02-15 | $7700.00 | Window Closed / Lapsed |