Timing circuit for actuating a load in accurate relationship to two inputs

Claim 1

A TIMING CIRCUIT FOR ACTUATING A LOAD IN ACCURATE AND PREDETERMINED RELATIONSHIP TO THE OCCURRENCE OF EVENTS IN AT LEAST TWO DISTINCT INPUT SYSTEMS, COMPRISING IN COMBINATION: A UNIJUNCTION TRANSISTOR HAVING AN EMITTER AND TWO BASES AND BIASING MEANS CONNECTED TO ONE OF SAID BASES SO THAT A PREDETERMINED BIAS IS MAINTAINED THEREON; MEANS CONNECTING ONE OF SAID INPUT SYSTEMS TO SAID ONE BASE WHEREBY THE BIAS ON SAID ONE BASE CAN BE MODIFIED; A FIRST CAPACITOR AND A FIRST CHARGING CIRCUIT FOR SAID CAPACITOR, SAID FIRST CHARGING CIRCUIT BEING CONNECTED TO THE OTHER INPUT SYSTEM; A FIRST DISCHARGING CIRCUIT FOR SAID CAPACITOR INCLUDING A CONNECTION TO SAID EMITTER AND THENCE THROUGH THE OTHER BASE OF SAID UNIJUNCTION TRANSISTOR; A VOLTAGE LIMITING CIRCUIT CONNECTED TO SAID FIRST CAPACITOR FOR LIMITING THE MAXIMUM CHARGE THEREON; A SECOND CAPACITOR CONNECTED TO SAID EMITTER AND ACROSS A PORTION OF SAID DISCHARGING CIRCUIT TO MAINTAIN CONDUCTION OF SAID UNIJUNCTION TRANSISTOR UNTIL SAID FIRST CAPACITOR HAS DISCHARGED AT LEAST TO A PRESELECTED MINIMUM VALUE; A LOAD CONNECTED TO SAID DISCHARGING CIRCUIT; AND A SUPPLEMENTAL CHARGING CIRCUIT CONNECTED TO SAID SECOND CAPACITOR FOR ESTABLISHING A MINIMUM CHARGE THEREON WHEN SAID FIRST CHARGING CIRCUIT IS INEFFECTIVE.