Inverter clamping circuit

Claim 1

AN OUTPUT CLAMPING CIRCUIT FOR A PULSE WIDTH MODULATED INVERTER COMPRISING: A DIRECT CURRENT SOURCE, A FIRST SEMICONDUCTOR HAVING A FIRST CONTROL ELECTRODE AND A FIRST OUTPUT ELECTRODE, A SECOND SEMICONDUCTOR HAVING A SECOND CONTROL ELECTRODE AND A SECOND OUTPUT ELECTRODE, AN OUTPUT TRANSFORMER HAVING A PRIMARY AND A SECONDARY WINDING, SAID PRIMARY WINDING HAVING A CENTER TAP ELECTRICALLY CONNECTED TO SAID DIRECT CURRENT SOURCE, MEANS FOR ELECTRICALLY CONNECTING SAID PRIMARY WINDING ACROSS SAID FIRST AND SECOND OUTPUT ELECTRODES, MEANS FOR GENERATING A CONSTANT FREQUENCY SIGNAL HAVING VARIABLE PULSES AND VARIABLE DWELL TIMES AND APPLYING SAID CONSTANT FREQUENCY SIGNAL TO SAID FIRST AND SECOND CONTROL ELECTRODES FOR RENDERING SAID SEMICONDUCTORS ALTERNATELY CONDUCTIVE DURING SAID PULSES AND JOINTLY NONCONDUCATIVE DURING SAID DWELL TIMES, SEMICONDUCTOR MEANS RESPONSIVE TO SAID CONSTNT FREQUENCY SIGNAL AND ELECTRICALLY CONNECTED ACROSS SAID PRIMARY WINDING FOR REDUCING THE VOLTAGE ACROSS SAID PRIMARY WINDING DURING SAID DWELL TIMES, AND BIASING MEANS INCLUDING A REFERENCE VOLTAGE AND CONNECTED TO SAID SEMICONDUCTOR MEANS FOR CLAMPING SAID PRIMARY WINDING VOLTAGE TO SAID REFERENCE VOLTAGE WHEN BOTH SAID FIRST AND SECOND SEMICONDUCTORS ARE CUT OFF BY SAID CONSTANT FREQUENCY SIGNAL.