Squitter monitor module

Claim 1

A PULSE RATE MONITOR SYSTEM COMPRISING A PULSE PAIR DECODER INCLUDING A FIRST MONOSTABLE MULTIVIBRATOR RECEIVING BEACON REPLY PULSES FROM A DIRECTIONAL COUPLER, A DIFFERENTIATING CIRCUIT HAVING AN INPUT FROM SAID FIRST MONOSTABLE MULTIVIBATOR, A SECOND MONOSTABLE MULTIVIBRATOR HAVING AN INPUT FROM SAID DIFFERENTIATING CIRCUIT, AND A FIRST NAND GATE HAVING AN INPUT FROM SAID FIRST AND SECOND MONOSTABLE MULITVIBRATORS AND HAVING AN OUTPUT TERMINAL FOR PROVIDING DECODED VIDEO SIGNALS; A CONTROL AND RESET FLIP-FLOP FOR RECEIVING SIGNALS FROM A CLOCK PULSE GENERATOR, A FIRST NOR GATE COUPLED FOR RECEIVING SIGNALS FROM SAID FIRST NAND GATE AND FROM SAID CONTROL AND RESET FILP-FLOP, A BINARY COUNT DOWN CHAIN HAVING A PLURALITY OF FILP-FLOP STAGES EACH RESET BY SAID CONTROL AND RESET FLIP-FLOP, THE FIRST FLIP-FLOP IN SAID COUNT DOWN CHAIN RECEIVING AN INPUT FROM SAID FIRST NOR GATE, A SIGN FLIPFLOP COMPRISING A REGISTER WITH SAID COUNT DOWN CHAIN, A SECOND NOR GATE HAVING INPUTS FROM THE LAST FOUR FLIPFLOPS IN THE SAID COUNT DOWN CHAIN AND FROM SAID SIGN FLIP-FLOP, A DIGITAL-TO-ANALOG CONVERTER HAVING INPUTS FROM SAID SECOND NOR GATE AND FROM A PLURALITY OF FLIP-FLOPS WHICH ARE INTERMEDIATE STAGES OF SAID COUNT DOWN CHAIN, A SQUITTER COUNT INDICATING METER FED BYS AID DIGITAL-TOANALOG CONVERTER, A SECOND AND A THIRD NAND GATE EACH HAVING INPUTS FROM FLIP-FLOPS WHICH ARE INTERMEDIATE TO SAID INTERMEDIATE STAGES OF THE COUNT DOWN CHAIN, A FOURTH NAND GATE HAVING INPUTS FROM SAID SECOND AND THIRD NAND GATES, FROM SAID SECOND NOR GATE, AND FROM SAID PULSE GENERATOR, A TIME DELAY CIRCUIT HAVING AN INPUT FROM SAID FOURTH NAND GATE, AND AN ALARM CIRCUIT FED BY SAID SQUITTER RATE DEVICE, SAID ALARM CIRCUIT COMPRISING A SILICON CONTROLLED RECTIFIER BEING TRIGGERED BY SAID FOURTH NAND GATE, AN ALARM RELAY FED BY SAID SILICON CONTROLLED RECTIFIER, AND AN ALARM LAMP CONTROLLED BY SAID ALARM RELAY.