Gated unijunction transistor oscillator having improved periodicity

Claim 1

A GATED UNIJUNCTION TRANSISTOR OSCILLATOR ENERGIZABLE BY A SUITABLE VOLTAGE SOURCE, SAID OSCILLATOR COMPRISING A UNIJUNCTION TRANSISTOR AND A RESISTIVE CAPACITIVE TIMING CIRCUIT HAVING A TIMING CAPACITOR COUPLED BETWEEN THE UNIJUNCTION TRANSISTOR EMITTER TERMINAL AND A COMMON JUNCTION, A GATING CIRCUIT CONNECTED IN A CAPACITOR BYPASS PATH TO THE COMMON JUNCTION TO HOLD SAID CAPACITOR AT A PREDETERMINED STARTING VOLTAGE DURING BYPASS GATING OPERATION, A NORMALLY NONCONDUCTIVE BYPASS CIRCUIT HAVING VOLTAGE DROP CHARACTERISTICS SUBSTANTIALLY IDENTICAL TO THOSE OF SAID GATING CIRCUIT AND PROVIDING ANOTHER CAPACITOR BYPASS PATH TO THE COMMON JUNCTION, AND MEANS FOR OPERATING SAID BYPASS CIRCUIT TO CARRY CAPACITOR DISCHARGE CURRENT UNTIL THE CAPACITOR VOLTAGE SUBSTANTIALLY REACHES THE PREDETERMINED STARTING VOLTAGE FOLLOWING EACH FIRING OF SAID UNIJUNCTION TRANSISTOR.