Complementary j-k flip-flop using transistor logic

Claim 1

IN A BINARY CIRCUIT HAVING TRUE AND COMPLEMENT OUTPUTS AND FIRST AND SECOND TRIGGER NODES FOR SWITCHING THE BINARY CIRCUIT TO THE LOGIC "1" STATE AND TO THE LOGIC "0" STATE, RESPECTIVELY, THE COMBINATION OF: FIRST AND SECOND TRIGGER TRANSISTORS THE COLLECTORS OF WHICH ARE CONNECTED TO THE FIRST AND SECOND TRIGGER NODES, RESPECTIVELY, AND THE EMITTER OF WHICH ARE COMMON WITH A CLOCK INPUT TO THE BINARY CIRCUIT, FIRST AND SECOND TRIGGER CAPACITORS CONNECTED TO THE BASES OF THE FIRST AND SECOND TRIGGER TRANSISTORS, RESPECTIVELY, SUCH THAT WHEN THE POTENTIAL OF THE CLOCK INPUT IS LOWERED THE CAPACITORS WILL DISCHARGE AND PROVIDE BASE CURRENT TO THE RESPECTIVE TRIGGER TRANSISTORS AND TURN THE RESPECTIVE TRIGGER TRANSISTORS ON, FIRST AND SECOND CHARGING TRANSISTORS CONNECTED IN EMITTER-FOLLOWER CONFIGURATION FOR CHARGING THE RESPECTIVE FIRST AND SECOND TRIGGER CAPACITORS, AND FIRST AND SECOND LOGIC INPUT MEANS CONNECTED TO THE FIRST AND SECOND TRIGGER CAPACITORS, RESPECTIVELY, FOR SELECTIVELY, IN RESPONSE TO INPUT LOGIC LEVELS, DISCHARGING THE RESPECTIVE CAPACITORS TO THEREBY DISABLE THE RESPECTIVE TRIGGER TRANSISTORS.