US3557314A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frame synchronization circuit
Assignee: International Standard Electric Corp
•
Filing: 1968-01-11
•
Granted: 1971-01-19
•
Expires: 1988-01-11
Abstract
Abstract The framing code of a time division multiplex digital data is compared cyclically with the local framing timing signals. When the comparison results in an out-of-frame condition, this condition is stored in a flip-flop and the results of the preceding j comparisons are stored in a j-stage shift register. A framing error signal is produced when the flip-flop and any k stages of the shift register simultaneously indicate an out-offrame condition. This error signal shifts the relative timing of the data and timing signals until an in-frame condition is produced by the comparison to inhibit the error signal.
Inventors
- 👤 Michel L Avignon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:16
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
333 words
A frame synchronization circuit for a time division multiplex digital data communication system comprising: a first source of received time division multiplex digital data including a framing signal; a second source of local timing signals during which said framing signal should be received; first means coupled to said first and second sources for periodic comparison of said framing signal and said local timing signals to produce a control signal having an in-frame condition and an out-of-frame condition; second means coupled to said first means to store said control signal resulting from a given plurality of said comparisons; third means coupled to said second means responsive to the simultaneous presence of a given number of said out-of-frame conditions of said control signal less than said given plurality of said comparisons to produce a framing error signal; fourth means coupled to said third means and at least one of said first and second sources responsive to said framing error signal to adjUst the relative timing of said received data and said local timing signals until said first means produces said control signal having said in-frame condition which enables the disabling of said second and third means; said second means including: a first bistable device coupled to said first means to store the results of the present one of said comparisons, and a j-stage shift register coupled to a given output of said first bistable device, said shift register having its count advanced by said first bistable device and store therein the results of the j previous ones of said comparison, where j is equal to an integer greater than one; and said third means including: logical decoder means coupled to said given output of said first bistable device and a predetermined output of each stage of said shift register to produce said framing error signal when said first bistable device and any k stage of said shift register stores simultaneously said out-of-frame condition, where k is an integer equal to or between one and j.
Claim 2
Dependent Claim
333 words
A frame synchronization circuit for a time division multiplex digital data communication system comprising: a first source of received time division multiplex digital data including a framing signal; a second source of local timing signals during which said framing signal should be received; first means coupled to said first and second sources for periodic comparison of said framing signal and said local timing signals to produce a control signal having an in-frame condition and an out-of-frame condition; second means coupled to said first means to store said control signal resulting from a given plurality of said comparisons; third means coupled to said second means responsive to the simultaneous presence of a given number of said out-of-frame conditions of said control signal less than said given plurality of said comparisons to produce a framing error signal; fourth means coupled to said third means and at least one of said first and second sources responsive to said framing error signal to adjUst the relative timing of said received data and said local timing signals until said first means produces said control signal having said in-frame condition which enables the disabling of said second and third means; said second means including: a first bistable device coupled to said first means to store the results of the present one of said comparisons, and a j-stage shift register coupled to a given output of said first bistable device, said shift register having its count advanced by said first bistable device and store therein the results of the j previous ones of said comparison, where j is equal to an integer greater than one; and said third means including: logical decoder means coupled to said given output of said first bistable device and a predetermined output of each stage of said shift register to produce said framing error signal when said first bistable device and any k stage of said shift register stores simultaneously said out-of-frame condition, where k is an integer equal to or between one and j.
Claim 3
Dependent Claim
31 words
A circuit according to claim 1, wherein said fourth means includes a second bistable device coupled to the output of said decoder means to control said adjustment of said relative timing.
Claim 4
Dependent Claim
56 words
A circuit according to claim 2, wherein: said second means further includes an INHIBIT gate having its inhibit input coupled to said first means and its output coupled to said first bistable device; said out-of-frame condition being represented by the absence of a signal; and said in-frame condition being represented by the presence of a signal.
Claim 5
Dependent Claim
47 words
A circuit according to claim 1, wherein said fourth means includes a phase corrector means coupled between said first source and said first means and coupled to the output of said decoder means responsive to said framing error signal to adjust the timing of said received data.
Claim 6
Dependent Claim
43 words
A circuit according to claim 4, wherein said fourth means further includes a second bistable device coupled to the output of said decoder means and the control input of said phase corrector to control said adjustment of said timing of said received data.
Claim 7
Dependent Claim
56 words
A circuit according to claim 5, wherein: said second means further includes an INHIBIT gate having its inhibit input coupled to said first means and its output coupled to said first bistable device; said out-of-frame condition being represented by the absence of a signal; and said in-frame condition being represented by the presence of a signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-18 | 1974-07-20 | 1975-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-18 | 1978-07-20 | 1979-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-18 | 1982-07-20 | 1983-01-19 | $7700.00 | Window Closed / Lapsed |