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US3558905A
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Fail-safe logical system
Assignee: KDDI Corp
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Filing: 1968-04-30
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Granted: 1971-01-26
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Expires: 1988-04-30
Abstract
Abstract A fail-safe logical system for performing general logical functions and for generating a predetermined logical output in case of fault of any element of any elemental circuit, wherein an 0-type input unit having an allowable failure-state of 0 and a 1 type input unit having an allowable failure-state of 1, are connected to a fail-safe logical unit which is formed by failsafe logical elemental circuits in accordance with the principle of alternate, cascade circuit arrangement, before and after a NOT circuit, to provide logical elemental circuits having different allowable failure-states.
Inventors
- 👤 Shintaro Oshima
- 👤 Teruji Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/007
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
123 words
In a fail-safe logical system including a fail-safe logical unit embodying fail-safe logical elemental circuits, wherein said system generates a predetermined logical output upon failure of any element of any of said elemental circuits, the improvement comprising: first input circuit means having a predetermined logical function and having means for generating only an 0 output condition upon entry of said first input circuit means into a failure state; and second input circuit means, having the same predetermined logical function as said first input circuit means, and having means for generating only a 1 output condition upon entry of said second input circuit means into a failure-state and in which said first and second input circuit means are connected to said fail-safe logical unit.
Claim 2
Dependent Claim
123 words
In a fail-safe logical system including a fail-safe logical unit embodying fail-safe logical elemental circuits, wherein said system generates a predetermined logical output upon failure of any element of any of said elemental circuits, the improvement comprising: first input circuit means having a predetermined logical function and having means for generating only an 0 output condition upon entry of said first input circuit means into a failure state; and second input circuit means, having the same predetermined logical function as said first input circuit means, and having means for generating only a 1 output condition upon entry of said second input circuit means into a failure-state and in which said first and second input circuit means are connected to said fail-safe logical unit.
Claim 3
Dependent Claim
59 words
A fail-safe logical system according to claim 1, in which the logical elemental circuits are connected in an alternate, cascade circuit arrangement, wherein at least one of said logical elemental circuits comprises a NOT circuit, and wherein the logical elemental circuits connected respectively to the input and output of each said NOT circuit have opposite 1 and 0 failure-states.
Claim 4
Dependent Claim
67 words
A fail-safe logical system according to claim 1, in which a pair of said logical elemental circuits comprise means for performing the same function and have different failure-states 0 and 1, respectively, from each other, and in which said logical elemental circuits include error detecting circuit means connected to said pair of logical elemental circuits, for detecting whether said pair of circuits have the same output state.
Claim 5
Dependent Claim
92 words
A fail-safe logical system according to claim 1, in which one of said fail-safe elemental circuits is a parametron element having input means, and further comprising signal means connected to said parametron element for applying a constant signal to said separate oscillation circuit, the constant signal having a predetermined phase-position 0 or pi with respect to a signal at said input means, and for applying an effective field to said parametron having an intensity which differs from the normal intensity of a field caused by input signals applied to the input means.
Claim 6
Dependent Claim
22 words
A fail-safe logical system according to claim 4, in which the constant signal is commonly applied to a plurality of parametron elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-25 | 1974-07-27 | 1975-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-25 | 1978-07-27 | 1979-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-25 | 1982-07-27 | 1983-01-26 | $7700.00 | Window Closed / Lapsed |