US3571616A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit
Assignee: Honeywell Inc
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Filing: 1969-06-18
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Granted: 1971-03-23
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Expires: 1989-06-18
Abstract
Abstract A semiconductor logic circuit adapted for fabrication as a monolithic circuit component. The circuit includes a multiemitter input transistor coupled to a phase splitter transistor which, in turn, connects to a pair of complementary operated output transistors. The circuit further includes slope control circuitry integrally fabricated therein.
Inventors
- 👤 John R Andrews
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K5/00; H03K5/01
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
206 words
A logic circuit comprising: a. a transistor gating means having a plurality of input terminals and an output terminal; b. a phase splitter transistor having its base electrode coupled to the output terminal of said transistor gating means and adapted to receive signals from said transistor gating means; c. an emitter resistor connecting the emitter electrode of said phase splitter transistor to a reference point; d. an output terminal; e. a source of DC potential; f. first and second complementary operated transistor switching means connected in series through said output terminal, said series connected switching means being coupled between said source of DC potential and said reference point, said first transistor switching means having its input coupled to the collector electrode of said phase splitter transistor and said second transistor switching means having its input coupled to the emitter electrode of said phase splitter transistor; g. a PN junction capacitor coupled between the emitter electrode of said phase splitter transistor and the emitter electrode of said first transistor switching means; and h. a diode connected between said first and second tRansistor switching means, said diode being adapted to provide operation for said capacitor over the substantially reverse-biased region of the voltage capacitance curve of said capacitor.
Claim 2
Dependent Claim
206 words
A logic circuit comprising: a. a transistor gating means having a plurality of input terminals and an output terminal; b. a phase splitter transistor having its base electrode coupled to the output terminal of said transistor gating means and adapted to receive signals from said transistor gating means; c. an emitter resistor connecting the emitter electrode of said phase splitter transistor to a reference point; d. an output terminal; e. a source of DC potential; f. first and second complementary operated transistor switching means connected in series through said output terminal, said series connected switching means being coupled between said source of DC potential and said reference point, said first transistor switching means having its input coupled to the collector electrode of said phase splitter transistor and said second transistor switching means having its input coupled to the emitter electrode of said phase splitter transistor; g. a PN junction capacitor coupled between the emitter electrode of said phase splitter transistor and the emitter electrode of said first transistor switching means; and h. a diode connected between said first and second tRansistor switching means, said diode being adapted to provide operation for said capacitor over the substantially reverse-biased region of the voltage capacitance curve of said capacitor.
Claim 3
Dependent Claim
23 words
A logic circuit as defined in claim 1 wherein the anode of said diode connects to one side of said p-n junction capacitor.
Claim 4
Dependent Claim
63 words
A logic circuit as defined in claim 1 and further comprising a feedback resistor connected between said output terminal and the emitter electrode of said phase splitter transistor to form a voltage divider with said emitter resistor, said feedback resistor being adapted to bias said second transistor switching means to a point immediately below the switching threshold of said second transistor switching means.
Claim 5
Dependent Claim
196 words
A logic circuit comprising: a. a multiple emitter transistor having its base electrode coupled to a DC power source; b. a plurality of input terminals each one connected to a separate emitter of said multiple emitter transistor and each adapted to receive a bi-level logic signal; c. a phase splitter transistor having its base coupled to the collector electrode of said multiple emitter transistor, its collector electrode coupled to a power source and its emitter electrode coupled to ground; d. a third transistor having its base coupled to the collector electrode of said phase splitter transistor and its collector electrode coupled to said power source; e. a fourth transistor having its emitter electrode grounded and its base electrode coupled from the emitter electrode of said phase splitter transistor; f. a PN junction capacitor coupled between the emitter electrode of said phase splitter transistor and the emitter electrode of said third transistor; and g. a diode connecting between the emitter electrode of said third transistor and the collector electrode of said fourth transistor, said diode being adapted to provide operation for said capacitor over the substantially reverse biased region of the voltage capacitance curve of said capacitor.
Claim 6
Dependent Claim
196 words
A logic circuit comprising: a. a multiple emitter transistor having its base electrode coupled to a DC power source; b. a plurality of input terminals each one connected to a separate emitter of said multiple emitter transistor and each adapted to receive a bi-level logic signal; c. a phase splitter transistor having its base coupled to the collector electrode of said multiple emitter transistor, its collector electrode coupled to a power source and its emitter electrode coupled to ground; d. a third transistor having its base coupled to the collector electrode of said phase splitter transistor and its collector electrode coupled to said power source; e. a fourth transistor having its emitter electrode grounded and its base electrode coupled from the emitter electrode of said phase splitter transistor; f. a PN junction capacitor coupled between the emitter electrode of said phase splitter transistor and the emitter electrode of said third transistor; and g. a diode connecting between the emitter electrode of said third transistor and the collector electrode of said fourth transistor, said diode being adapted to provide operation for said capacitor over the substantially reverse biased region of the voltage capacitance curve of said capacitor.
Claim 7
Dependent Claim
70 words
A logic circuit as defined in claim 4 further comprising a first resistor connecting between the collector electrode of said fourth transistor and the emitter electrode of said phase splitter transistor, and a second resistor connected between the emitter electrode of said phase splitter transistor and ground, said first and second resistors adapted to bias said fourth transistor into a state near conduction when said fourth transistor is substantially off.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-22 | 1974-09-21 | 1975-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-22 | 1978-09-21 | 1979-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-22 | 1982-09-21 | 1983-03-23 | $7700.00 | Window Closed / Lapsed |