US3577089A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transmission time domain equalizer
Assignee: International Business Machines Corp
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Filing: 1966-01-14
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Granted: 1971-05-04
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Expires: 1986-01-14
Abstract
Abstract Apparatus for equalizing digital data which has been distorted in transmission. The value of the signal at each instant of time is delayed and modified by a weighting junction and added to the value of the signal input at the next instant of time in an analog adder. The output of the analog adder is applied to a series of cascaded digital correction devices, the outputs of which are each connected through weighting junctions and switches to the analog adder to control the equalization of the signal input. The equalized signal output is taken from the last of these cascaded correction devices.
Inventors
- 👤 Etienne Gorog
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:33
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/06; H03K5/065
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
267 words
A time domain equalizer for equalizing an input signal from a transmission line at sampling times preceding and following the main signal, where the input signal is composed of a main signal pulse to be detected, m prepulses preceding the main signal pulse, and n trailing pulses following the main signal pulse, comprising: a succession of m-1 correction elements connected in cascade, the first of said correction elements being connected to said transmission line; a first series of m-1 weighted junctions each having its input connected to the output of a different correction element, and each supplying a weighted output signal; analog adding means having an input connected to said transmission line and having additional inputs connected to each of the outputs of said weighted junctions for adding said input signal to each of said weighted output signals so that all but the first prepulses preceding the main signal appearing at the output of said analog adder are equalized; a control device for detecting the main signal pulse connected to the output of said analog adder; a succession of m+n-1 storage elements connected in cascade, the input of the first of said storage elements being connected to the output of said control device, and the output of the last of said storage elements constituting the equalizer output; a second series of m+n-1 weighted junctions each connected to the output of a different storage element and each connected to further additional inputs of said analog adding means so that all the trailing pulses following the main signal pulse appearing at the output of said analog adder are equalized.
Claim 2
Dependent Claim
267 words
A time domain equalizer for equalizing an input signal from a transmission line at sampling times preceding and following the main signal, where the input signal is composed of a main signal pulse to be detected, m prepulses preceding the main signal pulse, and n trailing pulses following the main signal pulse, comprising: a succession of m-1 correction elements connected in cascade, the first of said correction elements being connected to said transmission line; a first series of m-1 weighted junctions each having its input connected to the output of a different correction element, and each supplying a weighted output signal; analog adding means having an input connected to said transmission line and having additional inputs connected to each of the outputs of said weighted junctions for adding said input signal to each of said weighted output signals so that all but the first prepulses preceding the main signal appearing at the output of said analog adder are equalized; a control device for detecting the main signal pulse connected to the output of said analog adder; a succession of m+n-1 storage elements connected in cascade, the input of the first of said storage elements being connected to the output of said control device, and the output of the last of said storage elements constituting the equalizer output; a second series of m+n-1 weighted junctions each connected to the output of a different storage element and each connected to further additional inputs of said analog adding means so that all the trailing pulses following the main signal pulse appearing at the output of said analog adder are equalized.
Claim 3
Dependent Claim
28 words
The time domain equalizer of claim 1 wherein each of said m-1 correction elements consist of an analog delay element for delaying the input signal one sampling time.
Claim 4
Dependent Claim
28 words
The time domain equalizer of claim 1 wherein each of said m-1 correction elements consist of an analog delay element for delaying the input signal one sampling time.
Claim 5
Dependent Claim
45 words
The time domain equalizer of claim 2 wherein each of said m+n-1 storage elements consists of digital storage devices and wherein said control device effects the movement of digital data stored in each storage element from one storage element to another only at sampling times.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-03 | 1974-11-02 | 1975-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-03 | 1978-11-02 | 1979-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-03 | 1982-11-02 | 1983-05-04 | $7700.00 | Window Closed / Lapsed |