US3577194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital conversion circuit
Assignee: General Electric Co
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Filing: 1969-01-03
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Granted: 1971-05-04
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Expires: 1989-01-03
Abstract
Abstract An analog-to-digital conversion circuit is disclosed, which converts a varying analog signal to the nearest available digital value by the successive approximation technique. The circuit includes a summing mode for the analog and various digital voltages, followed by a chopper switch, AC amplifier, sample-andhold circuit, voltage comparator, and digital approximation control circuits. The advantageous results are high speed, excellent resolution and accuracy, and low drift characteristics.
Inventors
- 👤 Donald L Beall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:28
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
167 words
An analog-to-digital conversion circuit comprising a summing node point, means for applying an analog signal to said summing node point, and successive approximation means to apply selected digital values to said summing node point in a sequence for causing the summing node voltage to approach a given value for determining the closest digital approximation to the analog value, wherein the improvement comprises a chopper switch device connected between said summing node point and a point of reference potential, an amplifier having an input connected to said summing node point, a comparator circuit having a first input connected to the output of said amplifier, a sample-andhold circuit connected between said amplifier output and a second input of said comparator circuit, said sample-and-hold circuit being synchronized with said chopper switch device so as to sample when the chopper switch device is closed and held when the chopper switch device is open, and means connecting the output of said comparator circuit to said successive approximation means for effecting control thereof.
Claim 2
Dependent Claim
167 words
An analog-to-digital conversion circuit comprising a summing node point, means for applying an analog signal to said summing node point, and successive approximation means to apply selected digital values to said summing node point in a sequence for causing the summing node voltage to approach a given value for determining the closest digital approximation to the analog value, wherein the improvement comprises a chopper switch device connected between said summing node point and a point of reference potential, an amplifier having an input connected to said summing node point, a comparator circuit having a first input connected to the output of said amplifier, a sample-andhold circuit connected between said amplifier output and a second input of said comparator circuit, said sample-and-hold circuit being synchronized with said chopper switch device so as to sample when the chopper switch device is closed and held when the chopper switch device is open, and means connecting the output of said comparator circuit to said successive approximation means for effecting control thereof.
Claim 3
Dependent Claim
15 words
A circuit as claimed in claim 1, in which said amplifier is an AC amplifier.
Claim 4
Dependent Claim
46 words
A circuit as claimed in claim 1, in which said sample-and-hold circuit comprises a switch connected between said amplifier output and said second input of the comparator circuit, and a capacitor connected between said second input of the comparator circuit and a point of reference potential.
Claim 5
Dependent Claim
68 words
A circuit as claimed in claim 1, in which said analog signal is applied to said summing node point with a given electrical polarity, and in which said digital values are applied to said summing node point with an electrical polarity opposite that of said given polarity, whereby said closest digital approximation to the analog value is determined as the voltage at said summing node point approaches zero.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-03 | 1974-11-02 | 1975-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-03 | 1978-11-02 | 1979-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-03 | 1982-11-02 | 1983-05-04 | $7700.00 | Window Closed / Lapsed |