Ceramic memory amplifier

Claim 2

In a ferroelectric capacitor matrix including a plurality of ferroelectric capacitor memory means having first and second oppositely facing surfaces; each said first surface exhibiting the characteristic of providing a reactive impedance with respect to a corresponding second surface, the improvement for developing a substantially constant output signal regardless of the number of ferroelectric capacitor memory means and comprising: a plurality of electrically conductive bit lines each associated with one of said memory means and adapted to be electrically connected to the first surface of said associated one of said memory means; a common bit line connected to at least two said bit lines to provide a matrix output terminal; electrically conductive means for electrically connecting the second surface of each said memory means with a reference voltage; amplifier means having an input circuit connected to said matrix output terminal and output circuit means for carrying an output signal; and, impedance means exhibiting the characteristic of providing a reactive impedance substantially equal in value to said reactive impedance of a said first surface with respect to a said second surface; said impedance means being connected between said output circuit means and said input circuit of said amplifier so that the value of the output signal is substantially independent of the number of ferroelectric capacitor memory means connected between said common bit line and said reference voltage.

Claim 3

In a ferroelectric capacitor matrix as set forth in claim 1 wherein said capacitor matrix includes a plurality of rows each including at least one said ferroelectric capacitor memory means; each said memory means exhibiting the characteristic of storing binary 1 and binary 0 signals, as desired; and, said impedance means includes a capacitance means exhibiting a reactive impedance substantially equal in value to said reactive impedance of a said first surface with respect to a said second surface.

Claim 4

In a ferroelectric capacitor matrix as set forth in claim 2 wherein said amplifier means exhibits the characteristic of providing an amplification factor having a value in excess of 500.

Claim 5

In a ferroelectric capacitor matrix as set forth in claim 2 wherein said amplifier means exhibits the characteristic of providing an amplification factor having a value approaching infinity.

Claim 6

In a ferroelectric capacitor matrix as set forth in claim 2 wherein said impedance means is a feedback path connected between said output circuit means and said input circuit and includes a capacitance means having a reactive impedance equal in value to the value of said reactive impedance of a said first surface with respect to a said second surface.

Claim 7

A ceramic memory system comprising: a plurality of ceramic memory means each including: a ferroelectric storage capacitor memory plate having a first and a second surface, said plate adapted to be polarized in one of two stable states; said first surface exhibiting the characteristic of providing a capacitive reactance with respect to a corresponding second surface; and, driving means having a surface, said second memory plate surface and said driving means surface being aligned to face Each other, at least a portion of said second surface being secured to at least a portion of the surface of said driving means for transmitting mechanical forces to said memory plate to thereby stress said memory plate; a plurality of electrically conductive bit lines each associated with one of said memory means and adapted to be electrically connected to the first surface of said associated one of said memory means; a common bit line connected to at least two said bit lines to provide a matrix output terminal; amplifier means having an input circuit connected to said matrix output terminal and an output circuit means for carrying an output signal; and, impedance means exhibiting a capacitive reactance equal to substantially the value of said capacitive reactance of a said first surface with respect to a said second surface; said impedance means being connected between said output circuit means and said input circuit of said amplifier so that the value of the output signal is substantially independent of the number of ferroelectric capacitor memory means connected between said common bit line and said reference voltage.

Claim 8

A ceramic memory system comprising: a plurality of ceramic memory means each including: a ferroelectric storage capacitor memory plate having a first and a second surface, said plate adapted to be polarized in one of two stable states; said first surface exhibiting the characteristic of providing a capacitive reactance with respect to a corresponding second surface; and, driving means having a surface, said second memory plate surface and said driving means surface being aligned to face Each other, at least a portion of said second surface being secured to at least a portion of the surface of said driving means for transmitting mechanical forces to said memory plate to thereby stress said memory plate; a plurality of electrically conductive bit lines each associated with one of said memory means and adapted to be electrically connected to the first surface of said associated one of said memory means; a common bit line connected to at least two said bit lines to provide a matrix output terminal; amplifier means having an input circuit connected to said matrix output terminal and an output circuit means for carrying an output signal; and, impedance means exhibiting a capacitive reactance equal to substantially the value of said capacitive reactance of a said first surface with respect to a said second surface; said impedance means being connected between said output circuit means and said input circuit of said amplifier so that the value of the output signal is substantially independent of the number of ferroelectric capacitor memory means connected between said common bit line and said reference voltage.

Claim 9

A ceramic memory system as set forth in claim 6 wherein said plurality of ceramic memory means is a ferroelectric capacitor matrix and includes a plurality of rows each including at least one ferroelectric storage capacitor memory means; each said memory means exhibiting the characteristic of storing binary 1 and binary 0 signals, as desired; and, said impedance means includes a capacitance means exhibiting a capacitive reactance substantially equal in value to said capacitive reactance of a said first surface with respect to a said second surface.

Claim 10

In a ceramic memory system as defined in claim 7 wherein said amplifier means exhibits the characteristic of providing an amplification factor having a value in excess of 500.

Claim 11

In a ceramic memory system as defined in claim 7 wherein said amplifier means exhibits the characteristic of providing an amplification factor having a value approaching infinity.