US3581214A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Discretely variable time delay system having submultiple, additive, and alternative delay selection
Assignee: University of Utah Research Foundation Inc
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Filing: 1969-06-19
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Granted: 1971-05-25
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Expires: 1989-06-19
Abstract
Abstract A time-delay system wherein an input signal triggers the generation of an output signal or pulse that can be accurately controlled as to time delay relative to the input signal, and preferably also as to pulse width. In a preferred form of the invention, the system includes plural circuits the delayed output of a first of which triggers the second, and so forth. Selected time delays of the plural circuits are additive, when desired, and pulse width and polarity are to be predetermined in the final output stage. Switching means are provided to connect in desired fashion one or more selected circuits to the output of the system, and one-shot multivibrators and pulse shaping stages are preferably used in each circuit. Precision resistance-capacitance circuits preferably assist to provide a stepped sequence of time delays as to each respective circuit, and the sequence of respective circuits are preferably related in a submultiple, time-delay relationship.
Inventors
- 👤 Ben L Seegmiller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:06
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
155 words
A time-delay system including, in combination, first circuit means responsive to a first circuit input signal for generating a first circuit output signal commencing after the occurrence of said first circuit input signal by a first time delay, second circuit means coupled to said first circuit means and responsive to said first circuit output signal thereof for generating a second circuit output signal commencing after said first circuit output signal by a second time delay, said first and second circuit means each including selection means For selecting the magnitude of such delay in a respective stepped sequence of possible delays, the stepped sequence of one of said circuit means being a submultiple of the stepped sequence of the remaining circuit means, output circuit means for producing a final delayed output signal, and switching means for selectively coupling one, the other, and both additively, of said first and second circuit means to said output circuit means.
Claim 2
Dependent Claim
155 words
A time-delay system including, in combination, first circuit means responsive to a first circuit input signal for generating a first circuit output signal commencing after the occurrence of said first circuit input signal by a first time delay, second circuit means coupled to said first circuit means and responsive to said first circuit output signal thereof for generating a second circuit output signal commencing after said first circuit output signal by a second time delay, said first and second circuit means each including selection means For selecting the magnitude of such delay in a respective stepped sequence of possible delays, the stepped sequence of one of said circuit means being a submultiple of the stepped sequence of the remaining circuit means, output circuit means for producing a final delayed output signal, and switching means for selectively coupling one, the other, and both additively, of said first and second circuit means to said output circuit means.
Claim 3
Dependent Claim
134 words
A time-delay system including, in combination, first circuit means responsive to a first circuit input signal for generating a first circuit output signal commencing after the occurrence of said first circuit input signal by a first time delay, and second circuit means coupled to said first circuit means and responsive to said first circuit output signal thereof for generating a second circuit output signal commencing after said first circuit output signal by a second time delay, said system including output circuit means for producing a final output signal, and switch means for selectively coupling, alternatively, said first circuit means to said output circuit means, said second circuit means to said output circuit means, and said first circuit means through said second circuit means to said output circuit means, for producing said final output signal.
Claim 4
Dependent Claim
134 words
A time-delay system including, in combination, first circuit means responsive to a first circuit input signal for generating a first circuit output signal commencing after the occurrence of said first circuit input signal by a first time delay, and second circuit means coupled to said first circuit means and responsive to said first circuit output signal thereof for generating a second circuit output signal commencing after said first circuit output signal by a second time delay, said system including output circuit means for producing a final output signal, and switch means for selectively coupling, alternatively, said first circuit means to said output circuit means, said second circuit means to said output circuit means, and said first circuit means through said second circuit means to said output circuit means, for producing said final output signal.
Claim 5
Dependent Claim
22 words
Structure according to claim 2 wherein said output circuit means includes adjustable means for varying the time-duration of said final output signal.
Claim 6
Dependent Claim
108 words
A time-delay system including, in combination: first, second, and third circuit means each including means responsive to a respective input signal thereto for generating a delayed signal, said first and second circuit means each including adjustable means for varying the magnitude of such delay in a respective stepped sequence, the stepped sequence of said second circuit means being a submultiple of the stepped sequence of said first circuit means, output circuit means for producing a final output signal, and switching means for selectively coupling any one and also any combination of said first, second, and third circuit means to said output circuit for producing said final output signal.
Claim 7
Dependent Claim
108 words
A time-delay system including, in combination: first, second, and third circuit means each including means responsive to a respective input signal thereto for generating a delayed signal, said first and second circuit means each including adjustable means for varying the magnitude of such delay in a respective stepped sequence, the stepped sequence of said second circuit means being a submultiple of the stepped sequence of said first circuit means, output circuit means for producing a final output signal, and switching means for selectively coupling any one and also any combination of said first, second, and third circuit means to said output circuit for producing said final output signal.
Claim 8
Dependent Claim
21 words
Structure according to claim 4 wherein said final output circuit includes means for varying the time-duration of said final output signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |