Analog-to-digital cyclic forward feed successive approximation conversion equipment

Claim 1

Apparatus of the class described comprising in combination: a. an analog input section including an input line responsive to a first analog input signal, a feedback line responsive to a second analog signal, switch means interposed between said input line and said feedback line, and means causing said switch means to be periodically activated between a first and second condition; b. a first summing circuit having a pair of inputs and an output, one of said inputs being connected to said input line and the other of said inputs being connected to a bias signal source, c. a comparator having a pluraLity of inputs and an output, one of said inputs being coupled to said first summing circuit in a first condition of said switch means and being coupled to said feedback line in a second condition of said switch means, an analog-to-digital converter including a plurality of parallel resistors arranged in a ladder network and adapted to be enabled into or switched out of said network respectively for providing another input to said comparator whereupon a first reference signal impressed upon said network can be compared with the analog output signal from said first summing circuit, d. first register means responsive to the output of said comparator for sequentially enabling each of said plurality of resistors into said ladder network thereby altering the value of the first reference signal impressed upon said network until said first reference signal substantially corresponds in magnitude to said first summing circuit analog output signal applied to said comparator through said switch means in a first condition thereof, e. an output register connected to said first register means for remembering the values of those resistors enabled into said network so as to provide a coarse digital value for the first analog input signal from said input section through said switch means in a first condition thereof, f. a digital-to-analog converter network responsive to said first register means, g. a summing amplifier into which is fed the output of the digital-to-analog converter network as well as the first analog input signal applied to said input section, said summing amplifier being adapted to produce said second analog signal on said feedback line wherein said second analog signal is equal to the difference between said first analog signal and the output of said digital-to-analog converter amplified by a predetermined factor, h. the output of said summing amplifier being connected to said feedback line whereby said feedback line is adapted to feed back said second analog signal to said comparator through said switch means when the latter is activated to its said second condition, whereby said second analog signal may be compared to said first reference signal impressed across said analog-todigital converter to produce a fine digital value corresponding to said second analog signal in said memory register means, and i. logic means responsive to a portion of the fine digital value in said first register and a portion of said coarse digital value in said output register for adding these two portions together and for introducing the result to said output register, j. said analog-to-digital converter further including means for superimposing a second reference signal of opposite polarity over said first reference signal in response to a second analog input signal of opposite polarity to said first analog input signal applied to said input section and for applying to said comparator said superimposed second reference signal during the time said switch means is activated to its first condition, and k. means responsive to said superimposing means for indicating the polarity of said second analog input signal.