US3590229A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital differentiator
Assignee: ELECTRONICS LAB Inc
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Filing: 1968-03-28
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Granted: 1971-06-29
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Expires: 1988-03-28
Abstract
Abstract For use with a data source furnishing data repetitively in digital form, apparatus which furnishes the value, first derivative, and second derivative of the data. A clock determines the rate of operation, or Delta t. A first and then second value is stored and the difference represents the derivative. On repeating this, a second derivative is obtained. For the shortest representation, the difference signals are only the sign bit of the subtracted values.
Inventors
- 👤 Johnny M Humphreys
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:48
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F7/00; G06F7/60; G06F7/64; G06F7/66
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
159 words
A circuit apparatus for use with a flow of digitized multibit words of weighted values, comprising: a. first register means for receiving a first multibit word therein; b. second register means for receiving a second and subsequently occurring multibit word therein; c. subtractor means connected to said first and second register means for subtracting the words therein and obtaining a third word; d. third register means connected to said subtractor means for storing a word received therefrom; e. fourth register means for receiving and storing a word from said subtractor means, said word occurring after the word stored in said third register means; and f. second subtractor means connected to said third and fourth register means for subtracting the words therein and obtaining a word representative of the second derivative of the multibit words, the word from said second subtractor means being characterized in the faCt that it is comprised of fewer bits than that of the multibit words.
Claim 2
Dependent Claim
159 words
A circuit apparatus for use with a flow of digitized multibit words of weighted values, comprising: a. first register means for receiving a first multibit word therein; b. second register means for receiving a second and subsequently occurring multibit word therein; c. subtractor means connected to said first and second register means for subtracting the words therein and obtaining a third word; d. third register means connected to said subtractor means for storing a word received therefrom; e. fourth register means for receiving and storing a word from said subtractor means, said word occurring after the word stored in said third register means; and f. second subtractor means connected to said third and fourth register means for subtracting the words therein and obtaining a word representative of the second derivative of the multibit words, the word from said second subtractor means being characterized in the faCt that it is comprised of fewer bits than that of the multibit words.
Claim 3
Dependent Claim
60 words
The invention of claim 1 including a buffer means connected to said first and second register means for receiving a first word from said first register means and for subsequently transferring said first word to said second register means at a time at least partially coincident with storage of said second and subsequently occurring word in said second register means.
Claim 4
Dependent Claim
60 words
The invention of claim 1 including a buffer means connected to said third and fourth register means for receiving a third word from said third register means and for subsequently transferring said third word to said fourth register means at a time at least partially coincident with storage of said fourth and subsequently occurring word in said fourth register means.
Claim 5
Dependent Claim
46 words
The invention of claim 2 including a clock means connected with said buffer means for periodically operating said buffer means at a rate sufficient to transfer the first word from said first register means to said second register means prior to arrival of the second word.
Claim 6
Dependent Claim
53 words
The invention of claim 1 wherein the first flow of digitized multibit words each include a sign bit and bits of weighted value and further wherein said first and second register means includes multiple stages for receiving the bits thereof, and said second subtractor means forms an output which is a single bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-28 | 1974-12-28 | 1975-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-28 | 1978-12-28 | 1979-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-28 | 1982-12-28 | 1983-06-29 | $7700.00 | Window Closed / Lapsed |