Real time digital fourier analyzer

Claim 2

In a real time digital Fourier analyzer a digital arithmetic logic device including: multiplication means for multiplying a first quantity representing a coefficient from a Fourier series and a second quantity exp (-2 pi j/n); sign determining means for generating the sign of the product of said first and second quantities; first complementing means, connected to said multiplication means for one''s complementing the product of said quantities; modified complementing means, connected to said sign generating means, for two''s complementing a third quantity representing a coefficient from a second Fourier series and adding to it a correction factor for the one''s complement of the product of said first and second quantities; and adding means, connected to said first and to said modified complementing means for summing the third quantity and the product of the first and second quantities, producing a sign corrected fourth quantity representing a coefficient of a third Fourier series.

Claim 3

In a real time digital Fourier analyzer a digital arithmetic logic device which during each step of each cycle of the calculation multiplieS together a coefficient from a first Fourier series and a system constant exp(-2 pi j/n) and produces a coefficient of a third series including: multiplication means for multiplying the real and imaginary part of a first quantity representing a coefficient from a Fourier series and a second quantity exp(-2 pi j/n); sign generating means for generating the sign of the product of said first and second quantities; first complementing means, connected to said multiplication means, for one''s complementing the products of said quantities; modified complementing means, connected to said sign generating means, for two''s complementing the real and imaginary parts of a third quantity representing a coefficient from a second Fourier series and adding to it a correction factor for the one''s complement of the produce of said first and second quantities; first adding means, connected to said first and to said modified complementing means, summing the real and imaginary parts of a third quantity and the products of the first and second quantities producing the real and imaginary parts of fourth and fifth quantities representing the coefficients of the third Fourier series.

Claim 4

In a real time digital Fourier analyzer a digital arithmetic logic device which during each step of each cycle of the calculation multiplieS together a coefficient from a first Fourier series and a system constant exp(-2 pi j/n) and produces a coefficient of a third series including: multiplication means for multiplying the real and imaginary part of a first quantity representing a coefficient from a Fourier series and a second quantity exp(-2 pi j/n); sign generating means for generating the sign of the product of said first and second quantities; first complementing means, connected to said multiplication means, for one''s complementing the products of said quantities; modified complementing means, connected to said sign generating means, for two''s complementing the real and imaginary parts of a third quantity representing a coefficient from a second Fourier series and adding to it a correction factor for the one''s complement of the produce of said first and second quantities; first adding means, connected to said first and to said modified complementing means, summing the real and imaginary parts of a third quantity and the products of the first and second quantities producing the real and imaginary parts of fourth and fifth quantities representing the coefficients of the third Fourier series.

Claim 5

A digital arithmetic logic device as in claim 2 including: memory means supplying said first and second quantities to said multiplication means and said third quantity to said modified complementing means during each step of each cycle and storing the outputs of said first adding means, said memory means containing at the end of all said cycles, the coefficients of one Fourier series.

Claim 6

In a real time digital Fourier analyzer, an address generator wherein during each cycle of the calculation and each step within each cycle the addresses to which and from where a quantity is to be withdrawn and placed are specified including: first counter means indicating the step in the cycle at which the calculation is at and indicating a completion of a cycle by accumulating a specified number of steps; series counting means indicating the number of Fourier series existing at the end of that cycle; an address specifying means connected to said first computer means and being responsive to said indication of a completion of a cycle, and further connected to said series counting means for generating said addresses by producing a first address and a second address, said second address being equal to the sum of said first address and a quantity stored in said series counter.

Claim 7

In a real time digital Fourier analyzer, an address generator wherein during each cycle of the calculation and each step within each cycle the addresses to which and from where a quantity is to be withdrawn and placed are specified including: first counter means indicating the step in the cycle at which the calculation is at and indicating a completion of a cycle by accumulating a specified number of steps; series counting means indicating the number of Fourier series existing at the end of that cycle; an address specifying means connected to said first computer means and being responsive to said indication of a completion of a cycle, and further connected to said series counting means for generating said addresses by producing a first address and a second address, said second address being equal to the sum of said first address and a quantity stored in said series counter.

Claim 8

A real time digital Fourier analyzer which during each step of each cycle of the calculation forms from two coefficients of separate Fourier series a coefficient of a third series including: a digital arithmetic unit including: multiplication means multiplying the real and imaginary parts of a first quantity representing a coefficient from a Fourier series, and second quantity representing a system constant exp(-2 pi j/n); sign determining means for generating the sign of the products of said first and second quantities; first complementing means, for one''s complementing the products of said quantities; modified complementing means, connected to said sign determining means for two''s complementing the real and imaginary parts of a third quantity representing a coefficient from a second Fourier series and adding to it a correction factor for the one''s complement of the product of said first and second quantities; first adding means, connected to said first and modified complementing means, summing the real and imaginary parts of said third quantity and the products of the first and second quantities, producing the real and imaginary parts of fourth and fifth quantities representing the coefficients of the third Fourier series; memory means connected to said multiplication means to said sign determining means, to said modified complementing means, and to said first adding means for suppLying said first and second quantities to said multiplication means and said third quantity to said modified complementing means during each step of each cycle and storing the outputs of said first adding means, said memory means containing at the end of all said cycles the coefficients of one Fourier series; and address generator means specifying during each step of each cycle the addresses to which and from where a quantity is to be withdrawn from and placed in said memory means including: first counter means indicating the step in the cycle at which the calculation is at and indicating a completion of a cycle by accumulating a specified number of steps series counting means connected to said first counter means indicating the number of Fourier series existing at the end of cycle; an address specifying means connected to said memory means and being responsive to said first counter means for receiving said indication of a completion of a cycle, means for generating said addresses by producing a first address and a second address, said second address being equal to the sum of said first address and a quantity stored in said series counter.

Claim 9

A real time digital Fourier analyzer which during each step of each cycle of the calculation forms from two coefficients of separate Fourier series a coefficient of a third series including: a digital arithmetic unit including: multiplication means multiplying the real and imaginary parts of a first quantity representing a coefficient from a Fourier series, and second quantity representing a system constant exp(-2 pi j/n); sign determining means for generating the sign of the products of said first and second quantities; first complementing means, for one''s complementing the products of said quantities; modified complementing means, connected to said sign determining means for two''s complementing the real and imaginary parts of a third quantity representing a coefficient from a second Fourier series and adding to it a correction factor for the one''s complement of the product of said first and second quantities; first adding means, connected to said first and modified complementing means, summing the real and imaginary parts of said third quantity and the products of the first and second quantities, producing the real and imaginary parts of fourth and fifth quantities representing the coefficients of the third Fourier series; memory means connected to said multiplication means to said sign determining means, to said modified complementing means, and to said first adding means for suppLying said first and second quantities to said multiplication means and said third quantity to said modified complementing means during each step of each cycle and storing the outputs of said first adding means, said memory means containing at the end of all said cycles the coefficients of one Fourier series; and address generator means specifying during each step of each cycle the addresses to which and from where a quantity is to be withdrawn from and placed in said memory means including: first counter means indicating the step in the cycle at which the calculation is at and indicating a completion of a cycle by accumulating a specified number of steps series counting means connected to said first counter means indicating the number of Fourier series existing at the end of cycle; an address specifying means connected to said memory means and being responsive to said first counter means for receiving said indication of a completion of a cycle, means for generating said addresses by producing a first address and a second address, said second address being equal to the sum of said first address and a quantity stored in said series counter.

Claim 10

A digital arithmetic logic device as in claim 3 wherein said multiplication means include: first multiplication means multiplying the first quantity times increasing integer values forming a series of partial products; selection logic means, connected to said first multiplication means, choosing selected partial products according to numerical value of said second quantity; a second multiplication means, connected to said selection logic, producing the products of the real and imaginary parts of its first two quantities by combining the selected partial products of the first quantities multiplied by the appropriate powers of two.

Claim 11

A digital arithmetic logic device as in claim 5 wherein said multiplication means include: first multiplication means multiplying the first quantity times increasing integer values forming a series of partial products; selection logic means, connected to said first multiplication means, choosing selected partial products according to numerical value of said second quantity; a second multiplication means, connected to said selection logic, producing the products of the real and imaginary parts of its first two quantities by combining the selected partial products of the first quantities multiplied by the appropriate power of two.

Claim 12

A digital arithmetic logic device as in claim 3 including: third complementing means, whose input is connected to said first adding means and whose output is connected to said memory means, two''s complementing the final sums and producing a sign corrected sum.

Claim 13

A digital arithmetic logic device as in claim 5 including: third complementing means, whose input is connected to said first adding means and whose output is connected to said memory means, two''s complementing the final sums and producing a sign corrected sum.

Claim 14

A digital arithmetic logic device as in claim 8 including: sense logic means, connected to said third complementing means, indicating whether there is any leading one''s in the two highest order bit position in the corrected sums; shift control means, connected to said multiplication means and said sense logic, shifting all said second and third quantities removed from said memory means during a cycle one bit to the left if said sense logic did not detect a leading one in the previous cycle; and a counter registering the number of multiplication cycles in which said shifting occurs and, thereby, indicating the correct order of magnitude of the final calculations.

Claim 15

A digital arithmetic logic device as in claim 9 including: sense logic means, connected to said third complementing means indicating whether there is any leading one''s in the two highest order bit position in the corrected sums; shift control means, connected to said multiplication means and sAid sense logic, shifting all said second and third quantities removed from said memory means during a cycle one bit to the left if said sense logic did not detect a leading one in in the previous cycle; and a counter registering the number of multiplication cycles in which said shifting occurs and, thereby, indicating the correct order of magnitude of the final calculations.

Claim 16

An address generator as in claim 4 wherein said series counting means includes: shift register means shifting when said first counter means indicates that a cycle has been completed; second counter means increasing once in value stored for each step; and comparator means connected to said shift register means and to said counter means for comparing the contents read as a binary number of all but the most significant bit in said shift register means with the number stored in said counter means, and producing an output upon a comparison, said output causing said second counter means to be reset to zero.

Claim 17

An address generator as in claim 5 wherein said series counting means includes: shift register means shifting when said first counter means indicates that a cycle has been completed; second counter means increasing once in value stored for each step; and comparator means connected to said shift register means and to said counter means for comparing the contents read as a binary number of all but the most significant bit in said shift register means with the number stored in said counter means, and producing an output upon a comparison, said output causing said second counter means to be reset to zero.

Claim 18

An address generator as in claim 12 specifying the addresses for a D-L algorithm wherein said address specifying means includes: third counter means increasing once in value stored for each step of the calculation and returning to zero when said first counter means indicates an end of a cycle; second adding means connected to said third counter means for summing the contents of said shift register means read as a binary number with the contents of said second counter means; and gate means connected to said second adding means and said third counter means for replacing the contents of said third counter means with the contents of said second adder means when said comparator means produces an output; the contents of said third counter means supplying the address of said third quantity and the sum produced by said second adder means representing the address of said second quantity.

Claim 19

An address generator as in claim 13 specifying the addresses for a D-L algorithm wherein said address specifying means includes: third counter means increasing once in value stored for each step of the calculation and returning to zero when said first counter means indicates an end of a cycle; second adding means connected to said third counter means for summing the contents of said shift register means read as a binary number with the contents of said counter means; and gate means connected to said second adding means and said third counter means for replacing the contents of said third counter means with the contents of said second adder means when said comparator means produces an output; the contents of said third counter means supplying the address of said third quantity and the sum produced by said second adder means representing the address of said second quantity.

Claim 20

An address generator as in claim 12 including: 1 register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means connected to said shift register means and to said register summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means connected to said third adding means and to said register means for replacing the contents of said register means with the sum produced by saId third adding means when said comparator means produces an output; and crossover means connected to said register means and producing as its output the contents of said register means in reverse order, said output representing the address of said first quantity.

Claim 21

An address generator as in claim 13 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means connected to said shift register means and to said register means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means connected to said third adding means and to said register means for replacing the contents of said register means with the sum produced by said third adding means when said comparator means produces an output; and crossover means connected to said register means and producing as its output the contents of said register means in reverse order, said output representing the address of said first quantity.

Claim 22

An address generator as in claim 12 but specifying the addresses for a C-T algorithm wherein said address specifying means includes: third counter means increasing once in value stored for each step of the calculation and returning to zero when said first counter means indicates an end of a cycle; second adding means summing the contents of said shift register means read as a binary number with the contents of said second counter means; and gate means replacing the contents of said second counter means with the contents of said second adder means when said comparator means produces an output; the contents of said third counter means supplying the address of said third quantity and the sum produced by said second adder means representing the address of said second quantity and the contents of said first counter means indicating the address of the fourth quantity and output of said third adding means specifying said fifth address.

Claim 23

An address generator as in claim 13 but specifying the addresses for a C-T algorithm wherein said address specifying means includes: third counter means increasing once in value stored for each step of the calculation and returning to zero when said first counter means indicates an end of a cycle; second adding means summing the contents of said shift register means read as a binary number with the contents of said second counter means; and gate means replacing the contents of said second counter means with the contents of said second adder means when said comparator means produces an output; the contents of said third counter means supplying the address of said third quantity and the sum produced by said second adder means representing the address of said second quantity and the contents of said first counter means indicating the address of the fourth quantity and output of said third adding means specifying said fifth address.

Claim 24

An address generator as in claim 12 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means replacing the contents of said register means with the sum produced by said second adder means when said comparator means produces an output, the output of said register means representing the address of said first quantity.

Claim 25

An address generator as in claim 13 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means replacing the contents of said register means with the sUm produced by said second adder means when said comparator means produces an output, the output of said register means representing the address of said first quantity.

Claim 26

An address generator as in claim 14 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means replacing the contents of said register means with the sum produced by said second adder means when said comparator means produces an output; and crossover means connected to said register means and producing as its output the contents of said register means in reverse order, said output representing the address of said first quantity.

Claim 27

An address generator as in claim 15 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means replacing the contents of said register means with the sum produced by said second adder means when said comparator means produces an output; and crossover means connected to said register means and producing as its output the contents of said register means in reverse order, said output representing the address of said first quantity.

Claim 28

An address generator as in claim 14 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means replacing the contents of said register means with the sum produced by said second adder means when said comparator means produces an output, the output of said register means representing the address of said first quantity.

Claim 29

An address generator as in claim 15 including: register means whose contents are cleared when said first counter means indicates an end of a cycle; third adding means summing all the contents of said shift register means except for the highest order bit read as a binary number and the contents of said register means; second gate means replacing the contents of said register means with the sum produced by said second adder means when said comparator means produces an output, the output of said register means representing the address of said first quantity.