US3594766A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital converter including comparator circuits with internal logic
Assignee: Tektronix Inc
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Filing: 1969-01-24
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Granted: 1971-07-20
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Expires: 1989-01-24
Abstract
Abstract An analog to digital converter is described having a differential analog input and a plurality of parallel digital outputs which includes a plurality of comparator circuits, each including a pair of emitter coupled transistors having a pair of inputs and a pair of outputs. The inputs formed by the bases of one transistor in each of the comparator circuits are connected in sequence through a voltage divider to one input terminal of the converter and the outputs at the collectors of such one transistors are connected by internal logic in common with the outputs at the collectors of the other transistors in the next preceding comparator circuit so that only when both transistors are nonconducting is an output pulse transmitted to an output terminal of the converter. The converter may have 10 parallel outputs and be used to provide a decimal readout for a 10position rotary switch by applying a stairstep voltage whose steps correspond to the positions of such switch, as the analog input signal of the converter.
Inventors
- 👤 Barrie Gilbert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:45
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15073; H03M; H03M1/00; H03M1/12; H03M1/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
227 words
An analog to digital converter circuit, comprising: comparator means including a plurality of signal comparator circuits each having a pair of first and second inputs and a pair of first and second outputs, said comparator circuits being switching circuits connected so that one of said outputs is rendered conducting and the other output is rendered nonconducting when he comparator circuit switches; first bias means for applying substantially the same DC bias voltage to the first inputs of said comparator circuits, said first inputs of said comparator circuits all being connected in common to one input terminal of the converter circuit; second bias means for applying a plurality of different DC bias voltages to the second inputs of Said comparator circuits, said second inputs being connected in a sequence to another input terminal of the converter circuit so that their bias voltages successively increase; and internal logic means within the comparator means, for directly connecting the first outputs of the comparator circuits in common with the second outputs of successive comparator circuits in said sequence to provide a plurality of common outputs for the comparator means, and for producing an output pulse on one of the common outputs when the first output of one comparator circuit and the second output of another comparator circuit connected in common with said one common output are both of the same condition.
Claim 2
Dependent Claim
227 words
An analog to digital converter circuit, comprising: comparator means including a plurality of signal comparator circuits each having a pair of first and second inputs and a pair of first and second outputs, said comparator circuits being switching circuits connected so that one of said outputs is rendered conducting and the other output is rendered nonconducting when he comparator circuit switches; first bias means for applying substantially the same DC bias voltage to the first inputs of said comparator circuits, said first inputs of said comparator circuits all being connected in common to one input terminal of the converter circuit; second bias means for applying a plurality of different DC bias voltages to the second inputs of Said comparator circuits, said second inputs being connected in a sequence to another input terminal of the converter circuit so that their bias voltages successively increase; and internal logic means within the comparator means, for directly connecting the first outputs of the comparator circuits in common with the second outputs of successive comparator circuits in said sequence to provide a plurality of common outputs for the comparator means, and for producing an output pulse on one of the common outputs when the first output of one comparator circuit and the second output of another comparator circuit connected in common with said one common output are both of the same condition.
Claim 3
Dependent Claim
79 words
A converter circuit in accordance with claim 1 which also includes an input means for applying a differential analog input signal between the inputs of each comparator circuit so that when the voltage of the differential input signal exceeds the bias voltage applied by the second bias means to the second input of a comparator circuit the outputs thereof switch between conduction and nonconduction to produce a digital output pulse on one of the output terminals of said converter.
Claim 4
Dependent Claim
41 words
A converter circuit in accordance with claim 1 in which the second bias means includes a voltage divider having a plurality of taps for applying said different bias voltages with the voltage differences between adjacent taps being substantially the same values.
Claim 5
Dependent Claim
74 words
A converter circuit in accordance with claim 1 in which the comparator circuits each include a pair of first and second electronic switching devices respectively having their control electrodes connected as the first and second inputs, having their output electrodes connected as the first and second outputs of the comparator circuits, and having their common electrodes connected together so that when one of said pair of switching devices is conducting the other is nonconducting.
Claim 6
Dependent Claim
37 words
A converter circuit in accordance with claim 4 in which the first and second bias means apply substantially the same DC bias current to the control electrodes of all of the switching devices in the comparator circuits.
Claim 7
Dependent Claim
17 words
A converter circuit in accordance with claim 4 in which the switching devices are semiconductor switching devices.
Claim 8
Dependent Claim
40 words
A converter circuit in accordance with claim 5 in which the switch devices are transistors having their bases connected as the control electrodes, having their collectors connected as the output electrodes, and having their emitters connected as the common electrodes.
Claim 9
Dependent Claim
79 words
A converter circuit in accordance with claim 7 in which the input means includes a pair of input transistors connected as emitter follower amplifiers having their bases connected as inputs of the converter circuit with the emitter of one input transistor connected to one end of the voltage divider for applying input signals to the second inputs of the comparator circuits and with the emitter of the other input transistor connected to the first inputs of each comparator circuit.
Claim 10
Dependent Claim
33 words
A converter circuit in accordance with claim 1 in which the input means includes a source of input voltage signals which differ in voltage amplitude by an amount equal to said voltage difference.
Claim 11
Dependent Claim
52 words
A converter circuit in accordance with claim 9 in which the source of input voltages is controlled by a mechanical switch so that the input voltage signals represent the position of such switch by changes in their voltage amplitude, and the digital output signal are transmitted to a switch position readout means.
Claim 12
Dependent Claim
27 words
A converter circuit in accordance with claim 6 in which the semiconductor switching devices are provided as part of comparator circuits formed in a monolithic integrated circuit.
Claim 13
Dependent Claim
51 words
A converter circuit in accordance with claim 7 which also includes a plurality of output transistors each connected as an inverter amplifier with its base connected to one output of the comparator means, and a common source of DC supply current connecTed to the emitters of all of the output transistors.
References Cited (Backward Citations)
US2733432A
Cited
US3241135A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |