US3602834A
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Timing recovery circuits
Assignee: International Business Machines Corp
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Filing: 1970-06-18
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Granted: 1971-08-31
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Expires: 1990-06-18
Abstract
Abstract A timing recovery circuit based on the departure from the zero crossing of an analog signal is disclosed. The departure from the zero crossing is proportional to the amplitude of a sample taken at a time when an analog signal is expected to experience a zero crossing. The amplitude and polarity of the resulting signal are stored in a hold circuit which applies the signal to a means for determining the direction of a possible transition. In the meantime, the input signal is applied to a data decision circuit which may be a clocked flip-flop, for example, which samples the polarity of the analog signal half a bit time later than the first sampling of the analog signal. The resulting output (a ''''1'''' or a ''''0'''') is simultaneously applied to the means for determining the direction of a possible transition and to a means for determining if a transition has in fact occurred. The former is an inverting gate which, in response to the polarity of the output of the clocked flip-flop, provides at its output either the output of the sample and hold circuit or an inverted version thereof. The latter means consists of a delay device such as a one bit shift register to provide an output delayed by one bit and an exclusive OR gate, the terminals of which are connected to the input and output of the delay device. The OR gate provides an output only when the polarities of the samples at the input and output of the delay device are different. This circuit, in effect, makes a comparison between the polarity of a present bit and a previous bit to determine whether or not a transition has occurred. The output of the exclusive OR circuit and the inverting gate are applied to another gate. This gate is operative only if the exclusive OR provides an output indicating that a transition has occurred and the output of the inverting gate is applied to an averaging filter which provides a control signal for adjusting the frequency of a variable frequency oscillator; the zero crossing of which is to be synchronized with the zero crossings of the analog signal.
Inventors
- 👤 Gerald K Mcauliffe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:21
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
106 words
A timing recovery circuit comprising in combination, a variable frequency oscillator, detection means for providing an analog signal which undergoes polarity transitions, sampling means for providing first and second samples of said analog signal connected to said variable frequency oscillator and said detector means, first means connected to said sampling means for determining the direction of a possible transition, second means connected to said sampling means for determining if a transition has occurred, means responsive to said first and second means for providing an output when a transition has occurred, and means for applying said output to said variable frequency oscillator to change the frequency thereof.
Claim 2
Dependent Claim
106 words
A timing recovery circuit comprising in combination, a variable frequency oscillator, detection means for providing an analog signal which undergoes polarity transitions, sampling means for providing first and second samples of said analog signal connected to said variable frequency oscillator and said detector means, first means connected to said sampling means for determining the direction of a possible transition, second means connected to said sampling means for determining if a transition has occurred, means responsive to said first and second means for providing an output when a transition has occurred, and means for applying said output to said variable frequency oscillator to change the frequency thereof.
Claim 3
Dependent Claim
17 words
A timing recovery circuit according to claim 1 wherein said variable frequency oscillator is a voltage-controlled oscillator.
Claim 4
Dependent Claim
42 words
A timing recovery circuit according to claim 1 wherein said sampling means includes a first sampling gate for obtaining said first sample at a given time interval and a second sampling gate for obtaining said second sample at a later time interval.
Claim 5
Dependent Claim
78 words
A timing recovery circuit according to claim 1 wherein said first means for determining the direction of a possible transition includes gating means for providing one of two possible outputs, one output being the inverse of the other, said output being the same polarity and magnitude as said first sample when said second sample is of one polarity and of the opposite polarity and same magnitude as said first sample when said second sample is of opposite polarity.
Claim 6
Dependent Claim
87 words
A timing recovery circuit according to claim 1 wherein said second means for determining if a transition has occurred includes: a delay device connected to said sampling means for applying said second samples thereto to provide an output delayed by a desired amount, and an exclusive OR gate, the input terminals of which are connected to the input and output of said delay device, said OR gate providing an output only when the polarities of signals at the input and output of said delay device are different.
Claim 7
Dependent Claim
47 words
A timing recovery circuit according to claim 1 wherein said means responsive to said first and second means for providing an output includes a gate the control signal of which is derived from said second means and the output of which is derived from said first means.
Claim 8
Dependent Claim
30 words
A timing recovery circuit according to claim 1 wherein said means for applying an output includes an averaging filter connected to said means responsive to said first and second means.
Claim 9
Dependent Claim
30 words
A timing recovery circuit according to claim 4 further including means connected to said sampling means and said gating means for storing the polarity and magnitude of said first sample.
Claim 10
Dependent Claim
24 words
A timing recovery circuit according to claim 5 wherein said delay device is a shift register providing a delay equal to one bit time.
Claim 11
Dependent Claim
24 words
A tIming recovery circuit according to claim 5 wherein said delay device is a delay line providing a delay equal to one bit time.
Claim 12
Dependent Claim
17 words
A timing recovery circuit according to claim 7 wherein said means for averaging includes an RC integrator.
Claim 13
Dependent Claim
248 words
A timing recovery circuit comprising: a voltage-controlled oscillator, means for developing unequalized analog signal the positive and negative polarities of which in given time intervals are representative of digital data, first means for sampling said analog signal to obtain an output the amplitude and polarity of which represents the departure of said analog signal from zero at the sampling interval, means for storing said amplitude and polarity of said output of said first means for a given period after sampling, second means for sampling said analog signal at the end of said given period to obtain the polarity of said analog signal, means responsive to the polarity of said second sampling means for providing an output signal of the same amplitude and polarity as that held in said means for storing when said output of said second means is of one polarity and an output signal of the same amplitude but of opposite polarity as that held in said means for storing when said output of said second means is of another polarity, means for comparing the polarities of said analog signal at the end of said given time period with the polarity of a different analog signal at the end of a previous given time period to provide an output only when said polarities are different, and means responsive to said last-mentioned output for applying said output of said means responsive to the polarity of said second sampling means to control the frequency of said voltage-controlled oscillator.
Claim 14
Dependent Claim
248 words
A timing recovery circuit comprising: a voltage-controlled oscillator, means for developing unequalized analog signal the positive and negative polarities of which in given time intervals are representative of digital data, first means for sampling said analog signal to obtain an output the amplitude and polarity of which represents the departure of said analog signal from zero at the sampling interval, means for storing said amplitude and polarity of said output of said first means for a given period after sampling, second means for sampling said analog signal at the end of said given period to obtain the polarity of said analog signal, means responsive to the polarity of said second sampling means for providing an output signal of the same amplitude and polarity as that held in said means for storing when said output of said second means is of one polarity and an output signal of the same amplitude but of opposite polarity as that held in said means for storing when said output of said second means is of another polarity, means for comparing the polarities of said analog signal at the end of said given time period with the polarity of a different analog signal at the end of a previous given time period to provide an output only when said polarities are different, and means responsive to said last-mentioned output for applying said output of said means responsive to the polarity of said second sampling means to control the frequency of said voltage-controlled oscillator.
Claim 15
Dependent Claim
47 words
A timing recovery circuit according to claim 12 wherein said means responsive to the polarity of said sampling means includes an inverting gate, the input of which is connected to said means for storing and the control electrode of which is connected to said second sampling means.
Claim 16
Dependent Claim
75 words
A timing recovery circuit according to claim 12 wherein said means for comparing includes a delay device connected to said second sampling means to provide an output delayed by one bit time, and an exclusive OR gate, the input terminals of which are connected to the input and output of said delay device, said gate providing an output only when the polarities of signals at the input and output of said delay device are different.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |