Jk-flip-flop

Claim 2

A JK-flip-flop, comprising a master flip-flop, a slave flipflop, intermediate gate means for connecting the output of the master flip-flop to the input of the slave flip-flop in response to a zero signal from a clocK input terminal, first input gate means having an output terminal and a plurality of input terminals, second input gate means having an output terminal and a plurality of input terminals, means for connecting both J and K input signals to input terminals of the first input gate means, means for connecting a Q output terminal of the slave flip-flop to an input terminal of the first input gate means, means for connecting a Q output of the slave flip-flop to an input terminal of the second input gate means, means for connecting both J and K input signals to input terminals of the second input gate means, the first and input gate means each comprising means for establishing connections between each of the J and K inputs and the master flip-flop in response to a one-clock pulse signal and for the entire duration of the one-clock pulse signal.

Claim 3

A JK-flip-flop as claimed in claim 1, wherein said first input gate means comprises the first partial gate means for receiving the K and Q signals and a second partial gate for receiving the J and Q signals, the first and second partial gates having a common connection point for receiving a clock pulse input signal, the first and second partial gates comprising means for providing a one-output signal to a first input terminal of the master flip-flop in response to the concurrence of a one signal on the clock input terminal and either one signals on both the K and Q input terminals or 0 signals on the J and Q input terminals and for providing a O signal to the first input terminal of the master flip-flop in response to the concurrence of a 1 signal on the clock pulse input terminal and either a O input on the K input terminal and a 1 signal on the Q input terminal or a O input on the Q input terminal and a 1 input on the J input terminal, the second input gate means comprising a third partial gate means for receiving the J and Q signals and a fourth partial gate means for receiving the K and Q signals, the third and fourth partial gates having a common connection point for receiving the clock input signals, the third and fourth partial gates comprising means for providing a 1 output signal to a second input terminal of the master flip-flop in response to the concurrence of a 1 input from the clock input signal and either 1 input on the J and Q input terminals or O inputs on the K and Q input terminals and for providing a O output signal to the second input terminal of the master flip-flop in response to the concurrence of a 1 input from the clock pulse and either a O signal on the J input and a 1 signal on the Q input or a O signal on the Q input and a 1 signal on the K input.

Claim 4

A JK-flip-flop as claimed in claim 1, wherein each input gate means comprises four transistors each having base, collector and emitter terminals, a first and second of the transistors having parallel connected base emitter paths, the third transistor of each input gate means having a collector terminal connected to the base terminal of the first transistor in the corresponding gate means, the collector of the fourth transistor in each input gate means connected to the base of the second transistor in the corresponding gate means, wherein the K signal is connected to the base terminal of the third transistor in the first input gate means and to the base of the second transistor in the second gate means, wherein the J signal is connected to the base of the second transistor in the first input gate means and to the third transistor in the second input gate means, wherein the Q signal is connected to the base terminals of the first and fourth transistors in the first input gate Means, and wherein the Q signal is connected to the base terminals of the first and fourth transistors in the second input gate means.

Claim 5

A JK-flip-flop as claimed in claim 3, further comprising a fifth transistor connected to the collectors of the first and second transistors in each input gate means for connecting the collectors of the first and second transistors to a source of supply in response to a 1 signal from the clock pulse input.

Claim 6

A JK-flip-flop as claimed in claim 3, further comprising a fifth transistor having base emitter and collector terminals, means for connecting the emitter terminal of the fifth transistor to the collector terminals of the first and second transistors in each of the input gate means, means for connecting the collector of the fifth transistor to a source of bias potential, means for connecting the base of the fifth transistor to the clock pulse input, a sixth transistor, and means for connecting the inverse of the clock pulses through the sixth transistor to the intermediate gate means for establishing a connection between the master flip-flop and slave flip-flop in response to the O clock pulse input.