US3619737A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planar junction-gate field-effect transistors
Assignee: International Business Machines Corp
•
Filing: 1970-05-08
•
Granted: 1971-11-09
•
Expires: 1990-05-08
Abstract
Abstract A junction-gate field-effect transistor is provided with its channel extending from the source to the drain in a direction normal to the plane of the substrate. The length of the channel is thereby substantially shorter than where the channel extends parallel to the plane of the substrate. The shorter channel provides faster switching speed and increased transconductance of the transistor.
Inventors
- 👤 Te-Long Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:45
CPC Classifications
H; H10; H10D; H10D99/00; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D84/00; H10D84/80; H10D84/86; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/053; Y10S148/085; Y10S148/151
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
30 words
A field-effect transistor as recited in claim 1 and wherein said channel region extends lonGitudinally in a direction substantially perpendicular to said lateral dimension bounded by said two gate regions.
Claim 2
Dependent Claim
25 words
A field-effect transistor as recited in claim 2 wherein said channel region extends longitudinally in a direction substantially normal to the plane of the substrate.
Claim 3
Dependent Claim
144 words
A planar junction-gate field-effect transistor comprising: a planar semiconductor member having a substantially planar surface, a planar epitaxial layer on said member, a first annular gate region diffused in said layer, an annular source region diffused in said layer and being approximately concentric with said gate region, a second annular gate region diffused in said layer and being approximately concentric with said source drain, said epitaxial layer having material of relatively low impurity concentration and extending between and separating said source region from said gate regions, an annular drain region diffused in said layer and being approximately concentric with said annular regions, an annular channel region in said member and having a width bounded by said two gate regions and extending axially between said source and drain regions, and an annular isolation region diffused in said layer and surrounding and isolating said recited regions.
Claim 4
Dependent Claim
23 words
A field-effect transistor as recited in claim 4 wherein said channel region extends axially in a direction substantially normal to said planar surface.
Claim 5
Dependent Claim
169 words
A field-effect transistor comprising: a semiconductor substrate doped with an impurity imparting to the substrate a first polarity type, an epitaxial layer on said substrate, a first gate region in said layer and doped with an impurity imparting to said gate region said first polarity type, a source region in said layer and doped with an impurity imparting to the source region a second polarity type, a second gate region in said layer and doped with an impurity imparting to said second gate region said first polarity type, said epitaxial layer having material of relatively low impurity concentration and extending between and separating said source region from said gate regions, an annular drain region in said substrate and said layer and doped with an impurity imparting to said drain region said second polarity type, a channel region in said layer and having a width bounded by said two gate regions and extending longitudinally between said source and drain regions, and an isolation region surrounding and isolating said recited regions.
Claim 6
Dependent Claim
28 words
A field-effect transistor as recited in claim 6 wherein said channel region extends in a longitudinal direction substantially normal to said width bounded by said two gate regions.
Claim 7
Dependent Claim
235 words
A planar junction gate field-effect transistor comprising: a semiconductor substrate having a substantially planar configuration and doped with an impurity imparting to the substrate a first polarity type, an epitaxial layer formed on said substrate and doped with an impurity imparting to the layer a second polarity type opposite to said first polarity type, a first annular gate region diffused in said layer and doped with an impurity imparting to said gate region said first polarity type, an annular source region diffused in said layer and being approximately concentric with said region and doped with an impurity imparting to the source region said second polarity type, a second annular gate region diffused in said layer and being approximately concentric with said source region and doped with an impurity imparting to said second gate region said first polarity type, said epitaxial layer having material of relatively low impurity concentration and extending between and separating said source region from said gate regions, an annular drain region diffused in said layer and doped with an impurity imparting to said drain region said second polarity type, an annular channel region in said layer and having a width boUnded by said two gate regions and extending axially between said source and drain regions in a direction approximately normal to the plane of said substrate, and an annular isolation region diffused in said layer and surrounding and isolating said recited regions.
Claim 8
Dependent Claim
190 words
A planar junction-gate field-effect transistor comprising: a planar semiconductor substrate having a planar configuration and doped with an impurity imparting to the substrate a first polarity type, a planar epitaxial layer formed on said substrate and doped with an impurity imparting to the layer a second polarity type opposite to said first polarity type, a first gate region formed in said layer and doped with an impurity imparting to said gate region said first polarity type, a source region formed in said layer and doped with an impurity imparting to the source region said second polarity type, a second gate region diffused in said layer and doped with an impurity imparting to said second gate region said first polarity type, said epitaxial layer having material of relatively low impurity concentration and extending between and separating said source region from said gate regions, A drain region formed in said layer and doped with an impurity imparting to said drain region said second polarity type, an annular channel region in said layer and having a width bounded by said two gate regions, and an isolation region surrounding and isolating said recited regions.
Claim 9
Dependent Claim
24 words
A transistor as recited in claim 9 wherein said channel region extends longitudinally in a direction approximately normal to the plane of the substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |