US3623020A
Expired / Lapsed
US
⏱️ 0.0 years remaining
First-in first-out buffer register
Assignee: RCA Corp
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Filing: 1969-12-08
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Granted: 1971-11-23
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Expires: 1989-12-08
Abstract
Abstract A storage means receives, and stores in separate stages, the bits of serially transmitted digital data. The stored data is read out during the read-in period at a rate which may be equal to or slower than that of the input data and which may start at the time the first bit is received. Output gates coupled to the storage means stages are enabled, one at a time, to read out the stored bits in the same order in which they are received.
Inventors
- 👤 Roger Alain Mao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:26
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C19/00; G11C19/28; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
153 words
A circuit for receiving successive data bits of an input bit stream, said bits occurring at a first rate, and for reading the bits out at a second rate not greater than said first rate comprising, in combination: storage means having at least N storage locations, where N is at least equal to the number of bits in the stream; means responsive to the successive bits for storing them in different locations in said storage means; N output gates, each connected to a different storage means location; and means for energizing said output gates, one at a time, at a rate not greater than said first rate in the same order in which the bits are stored in the corresponding storage means locations, and starting at a time during which the bits are being stored, for reading-out the stored bits at said second rate in the same order in which they are received.
Claim 2
Dependent Claim
153 words
A circuit for receiving successive data bits of an input bit stream, said bits occurring at a first rate, and for reading the bits out at a second rate not greater than said first rate comprising, in combination: storage means having at least N storage locations, where N is at least equal to the number of bits in the stream; means responsive to the successive bits for storing them in different locations in said storage means; N output gates, each connected to a different storage means location; and means for energizing said output gates, one at a time, at a rate not greater than said first rate in the same order in which the bits are stored in the corresponding storage means locations, and starting at a time during which the bits are being stored, for reading-out the stored bits at said second rate in the same order in which they are received.
Claim 3
Dependent Claim
137 words
The combination as claimed in claim 1: wherein said storage means and said means responsive to the successive bits together comprise a first shift register, means for applying said bits at said first rate to the first stage of the register, and means for shifting the bits at said first rate from stage-to-stage to load the register; wherein said second rate is synchronous with and a fraction of said first rate; and wherein said means for energizing said output gates comprises an N stage second shift register, each of whose stages is coupled to a different one of said output gates, said second shift register being operated at a rate to produce, by selectively energizing said output gates, a readout of said data bits at said second rate during the time said bitS are shifted from stage-to-stage.
Claim 4
Dependent Claim
41 words
The combination as claimed in claim 2: further including a common output line; and wherein each of said N output gates is connected to said common line for producing thereon the readout of said data bits stored in said first register.
Claim 5
Dependent Claim
98 words
The combination as claimed in claim 3: wherein each of said N output gates comprises a single transistor operated as a transmission gate, said transistor having a control electrode and a conduction path whose conductivity is determined by the potential applied to said electrode; wherein the conduction path of each transistor is connected at one end to a different one of the stages of said shift register and at the other end to said common line; and wherein the control electrode of each transistor is connected to a different one of the stages of said second shift register.
Claim 6
Dependent Claim
30 words
The combination as claimed in claim 4: wherein each of said transistors comprises a metal-oxide insulated-gate field-effect transistor; and wherein said first and second registers comprise solely insulated-gate field-effect transistors.
Claim 7
Dependent Claim
83 words
The combination as claimed in claim 1: wherein said storage means comprises N flip-flops for storing said input bits, one flip-flop per storage location, wherein said means responsive to the successive bits includes a first shift register having N stages and N write-in gates, each gate being coupled to a different one of said register stages and each connected to a different one of said flip-flops; and wherein said means for energizing said output gate comprises a second shift register having N stages.
Claim 8
Dependent Claim
77 words
The combination as claimed in claim 6: further providing a common input line for carrying said input data bits connected to said write-in gates; and wherein said means responsive to successive bits includes clocking means coupled to said first register for operating said first register at said first rate for sequentially energizing said write-in gates one at a time, for causing successive bits in said data bit stream to be stored in successive stages of said flip-flops.
Claim 9
Dependent Claim
73 words
The combination as claimed in claim 7: further providing a common output line connected to said output gates; and wherein said means for energizing said output gates includes clocking means coupled to said second register for operating said second register at said second rate for sequentially energizing said output gates for causing the successive bits of data stored in said flip-flops to be read out on said output line at said second rate.
Claim 10
Dependent Claim
32 words
The combination as claimed in claim 8: wherein said clocking means for operating said first and second registers includes means for operating said registers at first and second independent and unrelated rates.
Claim 11
Dependent Claim
38 words
The combination as claimed in claim 8: wherein said clocking means for operating said first and second registers includes means for operating said second register at said second rate which is at most equal to said first rate.
Claim 12
Dependent Claim
148 words
A buffer register for receiving data at a first rate and reading-out the data at a second rate, comprising: an input line for carrying serially propagated input data pulses occurring at said first rate; an output line; N data storing elements for storing said input pulses in the order received, where N is an integer greater than one; first means operated at said first rate for serially coupling one of said storing elements at a time to said input line for storing, in each one of said elements, a different one of said input data pulses; and second means for serially coupling said storing elements one at a time to said output line, including means for operating said second means at said second rate and concurrently with the storing of said input data pulses, for propagating serially on said output line the data pulses stored in said elements.
Claim 13
Dependent Claim
148 words
A buffer register for receiving data at a first rate and reading-out the data at a second rate, comprising: an input line for carrying serially propagated input data pulses occurring at said first rate; an output line; N data storing elements for storing said input pulses in the order received, where N is an integer greater than one; first means operated at said first rate for serially coupling one of said storing elements at a time to said input line for storing, in each one of said elements, a different one of said input data pulses; and second means for serially coupling said storing elements one at a time to said output line, including means for operating said second means at said second rate and concurrently with the storing of said input data pulses, for propagating serially on said output line the data pulses stored in said elements.
Claim 14
Dependent Claim
88 words
The combination as claimed in claim 11: wHerein said first means includes a write shift register having a N stages and a corresponding number of write gates, each one of said gates being connected between a different one of said data storing elements and said input line; and wherein said second means including a read shift register having N stages and a corresponding number of read gates, each one of said read gates being connected between a different one of said data storing elements and said output lines.
Claim 15
Dependent Claim
31 words
The combination as claimed in claim 12: wherein each of said data storing element comprises a static flip-flop and wherein each of said buffer register stages comprises solely metal-oxide semiconductor devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |