US3623075A
Expired / Lapsed
US
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Asynchronous data decoder
Assignee: Motorola Solutions Inc
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Filing: 1969-10-16
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Granted: 1971-11-23
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Expires: 1989-10-16
Abstract
Abstract Digital information to be decoded is transmitted over a voice band transmission medium as a sequence of half-cycles of tone of different frequencies, with different frequency tones being utilized for mark and space data bits. Only a half-cycle is required for each data bit with a phase reversal occurring at each data bit. The incoming signals are transformed into a sequence of zero crossings with the pulse interval time duration between these zero crossings being compared with a local frequency standard. At the end of each pulse interval, the decision of whether or not a mark or space has been received is determined in accordance with the count stored in a counter driven by the local frequency standard. The counter then is reset, storing a new count during the next half-cycle signal received.
Inventors
- 👤 Stephen M Bench
- 👤 Thomas J Rollins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:50
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/24; H04L27/10; H04L27/14
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
346 words
A system for decoding a train of binary data bits encoded as a sequence of alternating opposite phases of half-cycles of waves of two different frequencies, half-cycles of waves of one frequency corresponding to one binary condition and half-cycles of waves of another frequency corresponding to the other binary condition, each binary data bit being represented by a single half-cycle wave including in combination: means responsive to the encoded train of binary data bits for producing a sequence of data pulses representative of the sequence of phase reversals of the half-cycles waves in the encoded train of binary data bits; clock means producing a sequence of clock pulses at a frequency greater than the highest frequency of the waves representing the two binary conditions in the encoded train of binary data bits; counter means reset to an initial count with each data pulse and responsive to the clock pulses for producing at least a first output signal corresponding to a first count of clock pulses and a second output signal corresponding to a second count of a higher number of clock pulses; first bistable means having set and reset states of operation; second bistable means having set and reset states of operation; means responsive to the first output signal of the counter means for driving the first bistable means to its set state of operation; means responsive to the second output signal of the counter means for driving the second bistable device to its set state of operation and for driving the first bistable device to its reset state of operation; first output gating means coupled with the first bistable device and being enabled by the first bistable device in its set state of operation; second output gating means coupled with the second bistable device and being enabled by the second bistable device in its set state of operation; and means responsive to each data pulse for producing an output pulse from the enabled one of the first and second output gating means and for resetting the first and second bistable devices to the reset states.
Claim 2
Independent Claim
346 words
A system for decoding a train of binary data bits encoded as a sequence of alternating opposite phases of half-cycles of waves of two different frequencies, half-cycles of waves of one frequency corresponding to one binary condition and half-cycles of waves of another frequency corresponding to the other binary condition, each binary data bit being represented by a single half-cycle wave including in combination: means responsive to the encoded train of binary data bits for producing a sequence of data pulses representative of the sequence of phase reversals of the half-cycles waves in the encoded train of binary data bits; clock means producing a sequence of clock pulses at a frequency greater than the highest frequency of the waves representing the two binary conditions in the encoded train of binary data bits; counter means reset to an initial count with each data pulse and responsive to the clock pulses for producing at least a first output signal corresponding to a first count of clock pulses and a second output signal corresponding to a second count of a higher number of clock pulses; first bistable means having set and reset states of operation; second bistable means having set and reset states of operation; means responsive to the first output signal of the counter means for driving the first bistable means to its set state of operation; means responsive to the second output signal of the counter means for driving the second bistable device to its set state of operation and for driving the first bistable device to its reset state of operation; first output gating means coupled with the first bistable device and being enabled by the first bistable device in its set state of operation; second output gating means coupled with the second bistable device and being enabled by the second bistable device in its set state of operation; and means responsive to each data pulse for producing an output pulse from the enabled one of the first and second output gating means and for resetting the first and second bistable devices to the reset states.
Claim 3
Dependent Claim
140 words
The combination according the claim 1, wherein the counter means is a binary counter set to a count of zero by the means responsive to each data pulse and wherein the first output signal of the binary counter is produced in a time interval less than the time interval required for one-half cycle of the wave of the highest frequency used to represent one of the two binary conditions and wherein the second output signal of the binary counter is produced in a time interval which is greater than the time interval for one-half cycle of said wave used to represent said one of the two binary conditions and which is less than the time interval for one-half cycle of the wave used to represent The other of the two binary conditions in the encoded sequence of binary data bits.
Claim 4
Dependent Claim
36 words
The combination according to claim 2 further including means responsive to the second bistable device in its set state of operation for inhibiting the driving of the first bistable device to its set state of operation.
Claim 5
Dependent Claim
126 words
The combination according to claim 1 further including a third output signal from the counter means, the third output signal corresponding to a count of clock pulses greater than the count of clock pulses required to produce the second output, the time interval required for the counter means to produce the third output signal after the initial count being greater than the time interval for one-half cycle of the wave used to represent said other of the two binary conditions in the encoded sequence of binary data bits; and means responsive to the third output signal of the counter means for resetting the second bistable device to the reset state and for inhibiting the application of further clock pulses to the input of the counter means.
References Cited (Backward Citations)
US3341779A
Cited
US3510780A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |