US3624528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital demodulator
Assignee: Motorola Solutions Inc
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Filing: 1970-06-23
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Granted: 1971-11-30
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Expires: 1990-06-23
Abstract
Abstract A digital demodulator for demodulating a received bit signal containing binary and timing information wherein the signal shifts between two levels. Transition detectors respond to shifts between the two levels to produce pulses. A pulse at the beginning of each bit period represents timing information and is followed by pulses representing binary information. The timing pulse energizes a monostable which in turn enables a bistable to count pulses occurring while the monostable is energized. The monostable remains energized for 75 percent of the bit period, and when the monostable is deenergized, the state of the bistable is sampled and stored by a shift register. The energization and deenergization of the monostable is used to produce first and second timing pulses. The binary information and timing pulses are used to operate a digital decoder.
Inventors
- 👤 Richard H Adlhock
- 👤 Gerald L Giacomino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:37
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
215 words
A circuit for demodulating a received bit signal containing binary and timing information wherein the signal shifts between two levels, the shifts or transitions at the beginning of each bit period representing timing and the transitions during a bit period representing binary information, such circuit including in combination, transition detection means for detecting the shifts in level of said received bit signals and producing in response thereto first pulses, monostable multivibrator means coupled to said transition detection means and responsive to said first pulses to produce a second signal including pulses of a predetermined duration shorter than said bit period, pulse generation means coupled to said monostable multivibrator means and responsive to said second signal to produce a first timing signal at the beginning of each pulse of said second signal and a second timing signal at the end of each pulse of said second signal, counter means coupled to said transition detection means, said monostable multivibrator means and said pulse generation means, said second signal pulses enabling said counter means, said counter means counting said first pulses while enabled, storage means coupled to said counter means and pulse generation means, said storage means enabled by said second timing signal to store the count in said counter, said first timing signal resetting said counter means.
Claim 2
Dependent Claim
215 words
A circuit for demodulating a received bit signal containing binary and timing information wherein the signal shifts between two levels, the shifts or transitions at the beginning of each bit period representing timing and the transitions during a bit period representing binary information, such circuit including in combination, transition detection means for detecting the shifts in level of said received bit signals and producing in response thereto first pulses, monostable multivibrator means coupled to said transition detection means and responsive to said first pulses to produce a second signal including pulses of a predetermined duration shorter than said bit period, pulse generation means coupled to said monostable multivibrator means and responsive to said second signal to produce a first timing signal at the beginning of each pulse of said second signal and a second timing signal at the end of each pulse of said second signal, counter means coupled to said transition detection means, said monostable multivibrator means and said pulse generation means, said second signal pulses enabling said counter means, said counter means counting said first pulses while enabled, storage means coupled to said counter means and pulse generation means, said storage means enabled by said second timing signal to store the count in said counter, said first timing signal resetting said counter means.
Claim 3
Dependent Claim
49 words
The circuit of claim 1 further including amplifier means for amplifying said received bit signal, filter means coupled to said amplifier to eliminate undesired signals, and shaping means coupled to said filter means and said transition detection means for coupling said received bit signal to said transition detecting means.
Claim 4
Dependent Claim
13 words
The circuit of claim 1 wherein said counter means is a binary counter.
Claim 5
Dependent Claim
13 words
The circuit of claim 3 wherein said binary counter is a bistable multivibrator.
Claim 6
Dependent Claim
13 words
The circuit of claim 1 wherein said storage means is a shift register.
Claim 7
Dependent Claim
67 words
The circuit of claim 1 wherein said transition detection means includes first and second differentiation means, said first differentiation means being responsive to said positive transitions of said received bit signal to produce second pulses, said second differentiation means being responsive to said negative transitions of said received bit signal to produce third pulses, and means combining said second and third pulses to produce said first pulses.
Claim 8
Dependent Claim
14 words
The circuit of claim 2 wherein said filter means is a low pass filter.
Claim 9
Dependent Claim
13 words
The circuit of claim 2 wherein said shaping means is a Schmitt trigger.
Claim 10
Dependent Claim
195 words
A circuit for demodulating a received bit signal containing binary and timing information wherein the received bit signal shifts between two levels, said shifts or transitions representing timing and binary information, such circuit including in combination, transition detection means for detecting said level shifts and producing in response thereto first pulses, first circuit means coupled to said transition detection means and responsive to particular first pulses to produce second signals including pulses of a predetermined duration, second circuit means coupled to said first circuit means and responsive to said second signals to produce a third and fourth signal, said third signal produced at the beginning of each pulse of said second signal, said fourth signal produced at the end of each pulse of said second signal, counter means Coupled to said transition detection means, said first circuit means and said second circuit means, said second signals enabling said counter means, said counter means counting said first pulses while enabled, third circuit means coupled to said counter means and second circuit means, said third circuit means enabled by said fourth signal to sample the state of said counting means, said third signal resetting said counter means.
Claim 11
Dependent Claim
195 words
A circuit for demodulating a received bit signal containing binary and timing information wherein the received bit signal shifts between two levels, said shifts or transitions representing timing and binary information, such circuit including in combination, transition detection means for detecting said level shifts and producing in response thereto first pulses, first circuit means coupled to said transition detection means and responsive to particular first pulses to produce second signals including pulses of a predetermined duration, second circuit means coupled to said first circuit means and responsive to said second signals to produce a third and fourth signal, said third signal produced at the beginning of each pulse of said second signal, said fourth signal produced at the end of each pulse of said second signal, counter means Coupled to said transition detection means, said first circuit means and said second circuit means, said second signals enabling said counter means, said counter means counting said first pulses while enabled, third circuit means coupled to said counter means and second circuit means, said third circuit means enabled by said fourth signal to sample the state of said counting means, said third signal resetting said counter means.
Claim 12
Dependent Claim
27 words
The circuit of claim 9 wherein said particular first pulses are produced in response to received bit signal shifts occurring at the beginning of each bit period.
Claim 13
Dependent Claim
14 words
The circuit of claim 9 wherein said first circuit means is a monostable multivibrator.
Claim 14
Dependent Claim
14 words
The circuit of claim 9 wherein said second circuit means includes pulse generation means.
Claim 15
Dependent Claim
13 words
The circuit of claim 9 wherein said counter means includes bistable multivibrator means.
Claim 16
Dependent Claim
14 words
The circuit of claim 9 wherein said third circuit means includes shift register means.
Claim 17
Dependent Claim
28 words
The circuit of claim 14 wherein said shift register means includes first and second stages for storing the state of said counter means during two successive bit periods.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-29 | 1975-05-31 | 1975-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-29 | 1979-05-31 | 1979-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-29 | 1983-05-31 | 1983-11-30 | $7700.00 | Window Closed / Lapsed |