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US3631309A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit bipolar memory cell

Assignee: SEMICONDUCTOR ELECT MEMORIES
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Filing: 1970-07-23
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Granted: 1971-12-28
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Expires: 1990-07-23
📄 Original PDF 🌐 Google Patents

Abstract

Abstract An integrated circuit bipolar memory cell having two crosscoupled NPN transistors is provided in adjacent isolated regions of a silicon chip. Each region containing a transistor may include a diode and a large collector load resistor in parallel. A small resistor is provided in series with the diode, either in the same region or a separately isolated region. If in the same region, the small resistor may be included in the diode branch that is in parallel with the large resistor or in series between the cathode region of the diode and on N+ collector contact of the transistor. The base of the transistor and the anode of the diode are formed by diffusion of P-type impurities in an N-type film which serves as a collector region. While two emitters are diffused into the base region of the transistor, the same diffusant is used to form an N+ region across the anode region of the diode to form the large resistor as a thin channel for current conduction from the anode to the N+ region of the collector. The small resistor is formed in the bulk material of the silicon chip either between the cathode region of the diode and the collector region or in a separately isolated region.

Inventors

  • 👤 Charles Frank Myers

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 22:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085; Y10S148/136

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 92 words
The combination of claim 1 wherein said film of semiconductor type material is provided on a substrate diffused with impurities of the other one of said N and P types with a localized region heavily diffused to a predetermined depth in said substrate on the face thereof interfacing with said collector region over a continuous area beneath the external terminal region of said diode and said base region of said transistor, and the space between said external terminal region and said base region to reduce the sheet resistance of said collector region.
Claim 2
Dependent Claim 91 words
The combination of claim 2 including: means for isolating a second region of said film; a portion of said second region diffused with impurities of the other one of said N and P types to a predetermined depth to form a resistor region; a pair of ohmic contacts on said resistor region spaced apart to provide a resistor between said pair of ohmic contacts; and means for connecting one ohmic contact of said pair of ohmic contacts to said fourth ohmic contact to provide a resistor in series with said diode.
Claim 3
Dependent Claim 127 words
The combination of claim 1 wherein said film of semiconductor type material is provided on a substrate diffused with impurities of the other one of said N and P type with a localized region heavily diffused to a predetermined depth in said substrate on the face thereof interfacing with said collector region with impurities of said given one of N and P types over a discontinuous area beneath the external terminal region of said diode and said base region of said transistor to reduce the sheet resistance of said collector region except in that portion of the collector region between said first and fourth ohmic contact, thereby providing a current path of predetermined resistance forming a small resistor connected between said diode and said first ohmic contact.
Claim 4
Dependent Claim 58 words
The combination of claim 4 wherein said fourth ohmic contact is on a side of said transverse region remote from said first ohmic contact, whereby said small resistor is provided in series with said diode between said fourth and fifth ohmic contacts such that said large resistor is in parallel with said series connected diode and small resistor.
Claim 5
Dependent Claim 37 words
The combination of claim 5 wherein said means for providing electrical continuity from said fifth ohmic contact to said first ohmic contact comprises a metallized conductor from said fifth ohmic contact directly to said first ohmic contact.
Claim 6
Dependent Claim 62 words
The combination of claim 6 wherein said first ohmic contact is provided on a region heavily diffused with impurities of the same type as said transverse region, and said transverse region extends over said external terminal region of said diode only laterally in a direction toward said base region and integral with said heavily diffused region provided for said first ohmic contact.
Claim 7
Dependent Claim 48 words
The combination of claim 4 wherein said fourth ohmic contact is on a side adjacent to said first ohmic contact, whereby said small resistor is provided in series with each of said diode and said large resistor, and said diode and said large resistor are connected in parallel.
Claim 8
Dependent Claim 72 words
The combination of claim 8 wherein said means for providing electrical continuity from said fifth ohmic contact to said first ohmic contact comprises an ohmic contact on said transverse region connected to said fifth ohmic contact, whereby a current path is provided from said fourth ohmic contact to said first ohmic contact through said transverse region and through the small resistor portion of said collector region when said diode is back bIased.
Claim 9
Dependent Claim 61 words
The combination of claim 7 wherein said first ohmic contact is provided on a region heavily diffused with impurities of the same type as said transverse region, and said transverse region extends over said external terminal region of said diode laterally in a direction toward said base region and integral with said heavily diffused region provided for said first ohmic contact.

References Cited (Backward Citations)

US3218613A Cited
US3537078A Cited
US3573573A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-12-27 1975-06-28 1975-12-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-12-27 1979-06-28 1979-12-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-12-27 1983-06-28 1983-12-28 $7700.00 Window Closed / Lapsed

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