Data-processing system having logical storage data register

Claim 2

In a data-processing system having a store, the improvement comprising: a data register connected to the output of said store for receiving words therefrom, said register including a plurality of bistable devices settable according to a logic function; control means operated in synchronism with cycling of said store for providing a first signal for resetting said register and for providing a second signal for setting said register in accordance with a word read from said store; said control means including means for indicating the need to combine two words from said store in accordance with said logic function; and selectively actuated means responsive to said means for indicating inhibiting said first signal whereby the setting action of a second word from said store provides a logical combination in said register with a first word that is already stored in said register.

Claim 3

The invention of claim 1 wherein: said selectively actuated means includes a settable and resettable latch, said latch being connected to said control element whereby said latch is set in response to setting said control element.

Claim 4

The invention of claim 1 wherein: said data register includes a control portion having output lines connected to said memory for providing address bits and a memory cycle initiating signal thereto.

Claim 5

In a data-processing system, the combination comprising: a read-only store containing a plurality of addressable locations each containing a word having data bits and a control bit, said store being operative to cycle through a memory cycle in response to a GO signal and address bits, to read out the word at the addressed location; a read-only store data register coupled to the output of said store for receiving words therefrom, said register including a data portion for receiving said data bits of a word, and a control portion for receiving said control bit, said portions including a plurality of settable and resettable latches, said latches being settable in accordance with the logical OR function; means connected to said register for applying reset signals thereto in synchronism with a memory cycle; selectively operated inhibiting means connected to said last-mentioned means for inhibiting the resetting of said data portion whereby the setting action of a plurality of words provides the logical OR combination of said plurality of words in said data portion; and means responsive to a control bit placed in said register for operating said inhibiting means.

Claim 6

In a data-processing system, the combination comprising: a read-only store containing a plurality of addressable locations each containing a word having data bits and a control bit, said store being operative to cycle through a memory cycle in response to a GO signal and address bits, to read out the word at the addressed location; a read-only store data register coupled to the output of said store for receiving words therefrom, said register including a data portion for receiving said data bits of a word, and a control portion for receiving said control bit, said portions including a plurality of settable and resettable latches, said latches being settable in accordance with the logical OR function; means connected to said register for applying reset signals thereto in synchronism with a memory cycle; selectively operated inhibiting means connected to said last-mentioned means for inhibiting the resetting of said data portion whereby the setting action of a plurality of words provides the logical OR combination of said plurality of words in said data portion; and means responsive to a control bit placed in said register for operating said inhibiting means.

Claim 7

The invention of claim 4 including: a second word source connected to said data register for supplying words thereto.