Interlaced-scan-developing half-line-delay circuit

Claim 1

In an electronic video system capable of playing a film on which a composite signal containing vertical synchronization pulses has been recorded, a circuit for producing a series of vertical synchronization pulses that are evenly spaced to facilitate the development of an interlaced scan comprising separating means for separating vertical synchronization pulses present in the composite signal by subtracting from the composite signal a signal from which periodic portions containing the vertical synchronization pulses have been removed, and delay means for delaying every second vertical synchronization pulse arranged to receive the output of said separating means, said delay means having first and second outputs, each output having one-half the frequency of the synchronization pulses contained in the composite signal, said first output being in phase with every second of said pulses contained in the composite signal and said second output being out of phase with each of the vertical synchronization pulses contained within the composite signal, whereby the combined first and second outputs of the delayed means form the desired series of unevenly spaced vertical synchronization pulses.