Off-delay solid-state timer systems

Claim 2

In an off-delay solid-state timer system, the combination comprising: an electric power source; a load adapted to be energized from said source; solid-state means connected in circuit with said source and said load and comprising semiconductor switching means for controlling energization and deenergization of said load; an on-off switch; means operable by said on-off switch for controlling said semiconductor switching means thereby to energize said load; timing means supplied from said source and operable by said onoff switch for controlling deenergization of said load a predetermined time interval after off-actuation of said switch; said timing means comprising an RC timing circuit and a programmable unijunction transistor responsive to said RC timing circuit at the end of a predetermined time interval for providing a control signal; static means responsive to said control signal for controlling deenergization of said load and for clamping said timing means to prevent recycling thereof; and means in said timing means affording cancellation of the timing function without affecting load energization.

Claim 3

The invention as defined in claim 1, wherein said on-off switch is connected across said timing means to provide positive resetting of the system upon closure thereof and to prevent inadvertent timeout thereof.

Claim 4

The invention defined in claim 1, wherein said timing means comprises: a resistance network supplied from said source for providing gate voltage to said programmable unijunction transistor; means connecting said RC timing circuit to said network and to the anode of said programmable unijunction transistor; and means connecting the cathode of said programmable unijunction transistor to said static means.

Claim 5

The invention defined in claim 1, wherein said static means comprises: a triode thyristor responsive to said control signal for rendering said semiconductor switching means nonconducting thereby to deenergize said load; and means operable when said triode thyristor is rendered conducting for clamping said timing means to prevent reoperation of the RC timing circuit therein.

Claim 6

The invention defined in claim 4, wherein said clamping means comprises: a unidirectional diode connected in series with said triode thyristor across said tiMing means.

Claim 7

The invention defined in claim 5, wherein: said electric power source is an alternating current source; and said static means comprises means connected to said alternating current source for providing a filtered DC supply for said triode thyristor to reduce the likelihood of false operation thereof.

Claim 8

The invention defined in claim 5, wherein said means operable by said on-off switch for controlling said semiconductor switching means thereby to energize said load comprises: means responsive to closure of said on-off switch for applying a reverse voltage on said triode thyristor for rendering it nonconducting thereby to enable operation of said semiconductor switching means to energize the load.

Claim 9

The invention defined in claim 7, wherein said means responsive to closure of said on-off switch for applying a reverse voltage comprises: a commutating capacitor connected across said unidirectional diode and being operable to charge when said triode thyristor is conducting; and said on-off switch upon closure connecting said commutating capacitor across said triode thyristor to turn the latter off, said commutating capacitor thereafter preventing transients from rendering said triode thyristor conducting while said on-off switch is closed.

Claim 10

The invention defined in claim 1, wherein said means affording cancellation of a timing operation comprising: a unidirectional diode connected in series with said on-off switch across the capacitor of said RC circuit to afford fast discharge of the capacitor when the on-off switch is closed; and a control capacitor connected across one branch of said resistance network for delaying the rate of voltage decrease on the gate of said programmable unijunction transistor thereby to insure that the latter will not be rendered conducting when a timing function is cancelled.

Claim 11

The invention defined in claim 1, wherein: said electric power source is an alternating current source; said semiconductor switching means comprises a semiconductor controlled rectifier; and said solid-state means includes a rectifier bridge connected between said source and said semiconductor controlled rectifier.

Claim 12

The invention defined in claim 1, wherein: said semiconductor switching means comprises a power transistor; said solid-state means includes a rectifier bridge connected between said source and said power transistor; and said system may be powered by either a DC or AC source.

Claim 13

The invention defined in claim 1, wherein said semiconductor switching means comprises: two semiconductor controlled rectifiers in series connection; said means operable by said on-off switch for controlling said semiconductor switching means thereby to energize said load comprising means operable when said on-off switch is closed for rendering both of said controlled rectifiers conducting and comprising: means responsive to reapplication of power to the system following power interruption while the load is energized for rendering both of said controlled rectifiers conducting thereby to reenergize the load; and means effective when power to the system is reapplied following power interruption while the load is not energized and said on-off switch is open for preventing firing of one of said controlled rectifiers thereby to maintain the load deenergized.

Claim 14

In an off-delay solid state timer system, the combination comprising: an alternating current source; a load adapted to be energized from said source; power switching means for completing the circuit from said source to said load and comprising a pair of semiconductor controlled rectifiers in series connection; a rectifier bridge supplied from said source for supplying full-wave rectified anode voltage to one of said controlled rectifiers; means comprising a rectifier supplied from said source for providing a filtered DC supply; means normally applying a firing signal to sAid one controlled rectifier; a timing circuit energized from said DC supply; and for completing the firing circuit to the gate of the other controlled rectifier; means supplying anode voltage to said other controlled rectifier from said DC supply; means responsive to closure of said on-off switch for providing a firing signal to other said controlled rectifier to energize the load; said system being operative under said load energized condition if power is interrupted and comes back on for firing both of said controlled rectifiers to reenergize the load; means responsive to opening of said on-off switch for initiating operation of said timing circuit; and means responsive to timeout of said timing circuit for shunting the firing signal from said one controlled rectifier to deenergize the load; and said system being operative under either said timing condition or said load deenergized condition if the power is interrupted and comes back on for preventing refiring of said other controlled rectifier thereby to maintain the load deenergized.

Claim 15

In an off-delay solid state timer system, the combination comprising: an alternating current source; a load adapted to be energized from said source; power switching means for completing the circuit from said source to said load and comprising a pair of semiconductor controlled rectifiers in series connection; a rectifier bridge supplied from said source for supplying full-wave rectified anode voltage to one of said controlled rectifiers; means comprising a rectifier supplied from said source for providing a filtered DC supply; means normally applying a firing signal to sAid one controlled rectifier; a timing circuit energized from said DC supply; and for completing the firing circuit to the gate of the other controlled rectifier; means supplying anode voltage to said other controlled rectifier from said DC supply; means responsive to closure of said on-off switch for providing a firing signal to other said controlled rectifier to energize the load; said system being operative under said load energized condition if power is interrupted and comes back on for firing both of said controlled rectifiers to reenergize the load; means responsive to opening of said on-off switch for initiating operation of said timing circuit; and means responsive to timeout of said timing circuit for shunting the firing signal from said one controlled rectifier to deenergize the load; and said system being operative under either said timing condition or said load deenergized condition if the power is interrupted and comes back on for preventing refiring of said other controlled rectifier thereby to maintain the load deenergized.