Method and circuit arrangement for the supervision of connections in storage-programmed telecommunication switching installations for binary, coded messages

Claim 3

The method defined in claim 1, comprising the further step of: interrogating, one time, each transmitter cell, containing the counter registration, in the store by step-by-step interrogation so that the interrogation processes are evenly distributed over an interrogation cycle.

Claim 4

The method defined in claim 1, comprising the further step of: interrogating, in each case at the beginning of an interrogation cycle, all transmitter cells in direct succession by successive interrogation.

Claim 5

The method defined in claim 1, comprising the further steps of: dividing all transmitter cells into several equal groups and interrogating, successively, the transmitter cells within a group, the groups being interrogated in a step-by-step manner.

Claim 6

The method defined in claim 4, comprising the further steps of: reading a transmitter cell to be interrogated in a first storage cycle, temporarily storing the contents thereof in the program control, and testing the counter registration and, upon the existence of the polarity to be supervised, increasing in a second storage cycle said counter registration with the storage operation OR.

Claim 7

The method defined in claim 5, comprising the further steps of: placing the counter registration of a transmitter cell to be interrogated on ''''1'''' with the storage operation OR in a first storage cycle independent from the stored polarity, testing in the program control the storage word temporarily stored in the program control, said storage word having not been changed, and one of the steps of increasing, in a second storage cycle, with the storage operation OR the counter registration of the transmitter cell, or releasing the connection, or interrogating the next transmitter cell, the selection of said steps being dependent on the stored polarity and the counter registration of the unchanged storage word.

Claim 8

The method defined in claim 1, wherein connections with a supervision period of T or 2T are to be supervised, and comprising the further steps of: interrogating and processing in a first interrogation cycle all transmitter cells and processing only those transmitter cells assigned to transmitters with supervision period T in the next following interrogation cycle.

Claim 9

The method defined in claim 1, wherein connections having supervision period of T or 2T are to be supervised, comprising the further steps of: resetting to zero the counter registration in transmitter cells which are assigned to transmitters, participating in a connection, with the supervision period 2T, said counter registration having reached the highest registration corresponding to supervision period T, recording in an intermediate store information about the time of first reaching of the highest counter registration, interrogating, once more, said transmitter cells during the following supervision period T and releasing the connection after a renewed reaching of the highest counter registration.

Claim 10

The method defined in claim 1, wherein connections with supervision periods of T or 2T are to be supervised, comprising the additional steps of: delaying connections with the supervision period 2T, after the reaching of the highest counter registration in transmitter cells which are assigned to transmitters participating in said connections, said connections being delayed by the supervision period T and, releasing saiD connections only if the counter registration remains unchanged.

Claim 11

The method defined in claim 1, comprising the additional step of: storing the information identifying the transmitters to be supervised together with the address of the receiver in each case, the direction of the polarity change and the counter registration, in the transmitter cell in each case.

Claim 12

The method defined in claim 1, comprising the additional steps of: storing the information identifying the transmitters to be supervised in an indication field within the store wherein a bit is permanently assigned to each transmitter cell to be interrogated, taking over in each case one storage cell of said indication field by the program control and interrogating only those transmitter cells wherein the registered bit is set on ''''1''''.

Claim 13

A circuit arrangement for supervising connections in storage-programmed telecommunications switching installations for binary coded messages, wherein the lines are connected into a line connection unit (LE) for receiving and transmitting polarity changes within the binary messages, and the connections between the transmitter and receivers are established or broken with the aid of a program control (PSt), wherein the said line connection unit and said program control unit communicate with a storage unit (SE) containing data and programs required to perform switching tasks, and wherein a storage area for the reception of a storage word is permanently assigned to each transmitter, said storage word containing, during a connection, an internal connection member identifying the receiver in each case, and information concerning the direction of the last polarity change, as well as concerning the registration of a counter reset to zero by each incoming polarity change, said storage word being read and tested by said program control within a specific time interval whereby the counter registration at one of the two possible directions of the last polarity change is increased by one, and upon the arrival at a predetermined counter registration, the release of the connection is initiated, comprising: a storage operation control (SOPS) containing a word input register (WER) for the reception of a word to be placed into the store, and a word output register (WAR) for the reception of a word read out of a storage cell, outlets of said registers being connected to a connection system (OE) connected to the storage inlet, with which the contents of the said registers are connectable in dependence on a control signal determining the manner of connection, storage operation register means (OPR), control system means (SST) for forming a control signal from the information stored in a storage operation register (OPR), said information being transmitted to said register (OPR) by either the programmed control or the line connection unit.

Claim 14

A circuit arrangement for supervising connections in storage-programmed telecommunications switching installations for binary coded messages, wherein the lines are connected into a line connection unit (LE) for receiving and transmitting polarity changes within the binary messages, and the connections between the transmitter and receivers are established or broken with the aid of a program control (PSt), wherein the said line connection unit and said program control unit communicate with a storage unit (SE) containing data and programs required to perform switching tasks, and wherein a storage area for the reception of a storage word is permanently assigned to each transmitter, said storage word containing, during a connection, an internal connection member identifying the receiver in each case, and information concerning the direction of the last polarity change, as well as concerning the registration of a counter reset to zero by each incoming polarity change, said storage word being read and tested by said program control within a specific time interval whereby the counter registration at one of the two possible directions of the last polarity change is increased by one, and upon the arrival at a predetermined counter registration, the release of the connection is initiated, comprising: a storage operation control (SOPS) containing a word input register (WER) for the reception of a word to be placed into the store, and a word output register (WAR) for the reception of a word read out of a storage cell, outlets of said registers being connected to a connection system (OE) connected to the storage inlet, with which the contents of the said registers are connectable in dependence on a control signal determining the manner of connection, storage operation register means (OPR), control system means (SST) for forming a control signal from the information stored in a storage operation register (OPR), said information being transmitted to said register (OPR) by either the programmed control or the line connection unit.

Claim 15

The circuit arrangement according to claim 12, additionally comprising: word register means (WR) located in the interrogating program control, means for reading each storage word out of a transmitter cell during an interrogation and transmitting same from the word output register (WAR) into said word register (WR) , operation control means (VUE), test logic (PL) for testing bits within a storage word, said logic being controlled into an operating condition by said operation control (VUE), said test logic including means for opening the transmission paths between the registers of the program control and between the store and the program control for the program effecting the interrogation of all transmitter cells each time the word register (WR) contains a storage word to be tested, said test logic (PL) further including means for changing the counter registration stored in the word register and to emit, after the counter has cycled, a control signal to the said operation control (VUE) causing the initiation of the release, and mEans for transmitting the storage word in said word register, when the counter has not cycled, into said word input register (WER), upon changed counter registration for the purpose of changing the counter registration of the word with equal address in the store .

Claim 16

The circuit arrangement according to claim 12, further comprising: address counter register means (AZR) located within said program control and means connecting said address counter register, through an address register of the program control, to the address register of the storage operation control (SOPS), means for causing, at the beginning of each interrogation cycle , the beginning address of the storage area receiving the transmitter cells to be stored in said address counter register, said operation control (VUE1) increasing the count in address counter register AZR at every step of the interrogation cycle by the distance between the addresses of the transmitter cells to be interrogated and releasing the reading out of the store at the transmitter cell addressed.

Claim 17

The circuit arrangement according to claim 14, wherein: said address counter register AZR is divided into a first register B for the reception of a fixed basis address, a second register for the counting of the groups of transmitter cells GZ and a third register, connected before said second register GZ for counting transmitter cells ZZZ within a group, switch-forward impulses of an operation control VUE1 are conveyed to the counter ZZZ which reaches the highest registration after the completion of a group, and places a one-bit store on ''''1'''', said test logic PL including means for recognizing this condition and transmitting a control signal to the operation control VUE1, which causes the communication of the address of the next command into the command counter BZ.

Claim 18

Circuit arrangement according to claim 13, wherein: the beginning address of a group of transmitter cells is transmitted in each case into a first register RC of the program control PSt, and the number of transmitter cells in the group is put into a second register RB of the program control, said register RC containing the beginning address, is connected with the address register ARP of the program control, an operation control VUE2 increases at each step of the interrogation program in each case the contents of the first register RC by a number corresponding to the distance of the transmitter cells in the store, and decreases the contents of the second register RB by ''''1'''', said test logic PL including means for determining the registration of said second register and upon a ''''0'''' registration transmitting control signal to the operation control VUE2.

Claim 19

The circuit arrangement according to claim 13, further comprising: first register means (RA) provided within the program control into which is transmitted at the beginning of each interrogation of a group of transmitter cells the address of the first storage cell of the indication field, means in an operation control (VUE3) for increasing the contents of said first register after resetting of the addressed indication cell by ''''1'''', and to effect the, at least partial, transmission of the storage word contained in this indication cell into a shift register within the program control, means for shifting contents of the shift register, counter means (RB) for counting each of the steps of the shift register, testing means (P) for recognizing a binary condition and for stopping counter (RB) upon recognition of a binary condition thereby identifying a supervision request of the indication bit appearing at the outlet of the shift register, and for preventing the continued counting of the counter (RB), the address of the transmitter cell, assigned to the indication bit, being formed with the aid of the first register (RA) and the counter (RB).

Claim 20

The circuit arrangement according to claim 17, wherein; an accumulator AK of the program control is used as the shift register, and the shift counter RB of the accumulator as the counter.

Claim 21

Circuit arrangement according to claim 17, wherein: the address of the transmitter cell is formed from the fixed contents of a basic register B, the last digits of the address of the indication cell in each case, stored in the said first register RA, and the contents of the said meter RB.