Apparatus and method for adjusting the indexing rate of a fixed length shift register

Claim 2

In combination: Apparatus adapted to generate a series of synchronizing pulses; Dynamic shift register means having a predetermined number of volatile storage cells, each capable of storing information only a predetermined short period of storage; Means for clocking said register means at a predetermined sampling rate for at least a first portion of the period between said synchronizing pulses; and Second means for clocking said register means, subsequent to said first portion of the period between said synchronizing pulses, with a mixture of fast and slow clocking pulses, said mixture being proportioned to cause said register to reach its end prior to, but within said period of storage of, said synchronizing pulses.

Claim 3

The combination recited in claim 1 in which said apparatus is a radar apparatus, and in which radar information is stored in said register during said first portion of the period between synchronizing pulses and is transferred through said register at said fast and slow rates so that the leading bit of information stored in said register reaches the end of said register prior to receipt of, but within said period of storage of, said synchronizing pulses.

Claim 4

The combination recited in claim 1 in which said apparatus is a sonar apparatus, and in which sonar information is stored in said register during said first portion of the period between synchronizing pulses and is transferred through said register at said fast and slow rates so that the leading bit of information stored in said register reaches the end of said register prior to receipt of, but within said period of storage of, said synchronizing pulses.

Claim 5

The combination recited in claim 1 in which said volatile storage cells comprise field-effect-transistors adapted to store information and signals for said short period of storage.

Claim 6

The combination of claim 4 in which said field-effect-transistors are metal-oxide-silicon types.

Claim 7

The combination recited in claim 1 and further comprising means for indicating the end of said first portion of the period between said synchronizing pulses.

Claim 8

The combination of claim 6 in which the period of time between the end of said first portion and the end of the period between said synchronizing pulses is characterized by said second clocking means clocking said register with separate groups of slow and fast pulses in either order.

Claim 9

The combination of claim 7 and further comprising means for controlling the time of change in pulse rate between said fast and slow pulses.

Claim 10

The combination of claim 8 in which said group of slow pulses precedes said group of fast pulses, and in which said apparatus generates a pre-trigger pulse which is connected to control the time of change of the pulse rate delivered to said register from slow to fast pulses.

Claim 11

The combination of claim 9 in which: said first portion of The period between said synchronizing pulses comprises a sample time, XtL; a second portion of said period comprises a slow clock time, YtS+P; a third portion of said period comprises a fast clock time, ZtF; a last portion of said period comprises a waiting period, W; and wherein X is the number of sampling pulses delivered to said register, tL is the time between said sampling pulses, Y is the number of slow pulses delivered to said register, tS is the time between said slow pulses, P is the time between the last said slow pulse and said pre-trigger pulse, Z is the number of fast pulses delivered to said register, tF is the time between said fast pulses, W is the time between the last said fast pulse and the said synchronizing pulse, X+Y+Z is the number of cells in said register, and W is less than said period of storage of said cells.

Claim 12

The combination of claim 10 and further comprising: A counter, connected to count the number of pulses delivered to said register, and connected to be zero-set by said synchronizing pulse; First gating means, adapted to be opened by said synchronizing pulse and to be closed by said counter after said counter counts X pulses, for gating pulses to said register at said sampling rate; Second gating means, adapted to be opened by said counter at the time said first gating means is closed and to be closed by said pre-trigger pulse, for gating pulses to said register at said slow rate; and Third gating means, adapted to be opened by said pre-trigger pulse and to be closed by said counter when the count in said counter equals the number of said cells, X+Y+Z, in said register, for gating pulses to said register at said fast rate.

Claim 13

The combination of claim 8 and further comprising: Means for sensing the reaching of the end of said register; Means for generating a first control signal when the said synchronizing pulse arrives before the end of said register is reached; Means for generating a second control signal when the end of said register is reached before, but within said period of storage of, said synchronizing pulse; Means for generating a third control signal when the end of said register is reached before, but not within said period of storage of, said synchronizing pulse; Means connected to be responsive to said first control signal to increase the number of said slow pulses while decreasing the number of said fast pulses between said synchronizing pulses; Means connected to be responsive to said second control signal to maintain the mix of said fast and slow pulses between said synchronizing pulses; and Means connected to be responsive to said third control signal to increase the number of said fast pulses while decreasing the number of said slow pulses between said synchronizing pulses.

Claim 14

The combination of claim 12 in which said group of fast pulses precedes said group of slow pulses.

Claim 15

The combination of claim 13 in which, when said second control signal is controlling: Said first portion of the period between said synchronizing pulses comprises a sample time, XtL; A second portion of said period comprises a fast clock time, ZtF; A third portion of said period comprises a slow clock time, YtS; A last portion of said period comprises a waiting period, W; and Wherein X is the number of sampling pulses delivered to said register, tL is the time between sampling pulses, Z is the number of fast pulses delivered to said register, tF is the time between said fast pulses, Y is the number of slow pulses delivered to said register, tS is the time between said slow pulses, W is the time between the lAst said slow pulse and the said synchronizing pulse, X+Z+Y is the number of cells in said register, and W is less than said period of storage of said cells.

Claim 16

The combination of claim 14 and further comprising: A clock counter, connected to count the number of sampling, fast, and slow pulses delivered, connected to be reset by said synchronizing pulses, and adapted to generate signals indicative of the end of the sampling pulses after X pulses have been delivered, the end of the register after X+Z+Y pulses have been delivered, and not to the end of the register before X+Z+Y pulses have been delivered; A control counter, gated to receive all fast and slow pulses delivered, enabled to be set to count Z+Y-1 pulses by said first control signal, enabled to be set to count Z+Y pulses by said second control signal, and enabled to be set to count Z+Y+1 pulses by said third control signal, said control counter generating an output signal when it reaches the end of its count. A vernier ring counter, gated to receive said fast and slow clocks, and adapted to generate an output signal when a predetermined bit position of said ring counter is energized; Means for gating pulses at said sampling rate to said clock counter and said register, opened in response to said synchronizing pulse and closed by a signal from said clock counter at the end of X pulses; Means for gating pulses at said fast rate to said clock counter and said register, opened by a signal from said clock counter at the end of X pulses and closed by an output signal from said ring counter. Means for gating pulses at said slow rate to said clock counter and said register, opened by an output signal from said ring counter and closed by said next synchronizing pulse if it occurs before the X+Z+Y count, and closed by an output signal from said control counter if it occurs after the X+Z+Y count and before the next synchronizing signal; and Means for inhibiting the transmission of pulses, in excess of X+Z+Y pulses, to said register.

Claim 19

In a system characterized by transmission of a pulse of energy in synchronism with a synchronizing pulse, and measurement of information by its timing relative to said synchronizing pulse, the returned information being stored in a dynamic register whose storage time is short compared to the time between synchronizing pulses, so that information generated by consecutive pulses can be compared, the improvement comprising: Means for revitalizing said information pending the receipt of the next synchronizing pulse; and Means for placing said revitalized information into positions in said register which are the same during successive intervals between synchronizing pulses so that the information can be compared with incoming information.

Claim 20

In a system characterized by transmission of a pulse of energy in synchronism with a synchronizing pulse, and measurement of information by its timing relative to said synchronizing pulse, the returned information being stored in a dynamic register whose storage time is short compared to the time between synchronizing pulses, so that information generated by consecutive pulses can be compared, the improvement comprising: Means for revitalizing said information pending the receipt of the next synchronizing pulse; and Means for placing said revitalized information into positions in said register which are the same during successive intervals between synchronizing pulses so that the information can be compared with incoming information.

Claim 21

Apparatus as recited in claim 17 in which said revitalized information is placed by indexing said information serially through said dynamic memory, including means for timing said indexing in series of fast and slow pulses, with the mix of said fast and slow pulses such that the leading bit of said information appears at the end of said register substantially in synchronism with said synchronizing pulse.