Noise discriminator for digital data detection system

Claim 2

A circuit for eliminating noise signals from a succession of binary bit signals comprising: a pair of channel means for passing bit signals between input and output ends thereof: separate first gating means associated with each of the pair of channel means for delaying the bit signals passed to the associated channel means by a period of time at least equal to the time duration of the noise signals to block noise signals occurring prior to the bit signals from the output end; and separate second gating means associated with each of the pair of channel means for inhibiting the passage of bit signals to the output end of the associated channel means for a selected period of time to block noise signals occurring after the bit signals from the output end; wherein the binary bit signals comprise transitions through zero of the waveform of a modified frequency modulated data signal having a succession of substantially uniform bit cells, the waveform of the data signal having a transition through zero substantially at the midpoint of each bit cell representing binary ''''1'''' and substantially at the leading edge of each bit cell which represents binary ''''0'''' and which is not preceded by a bit cell having a transition through zero at the midpoint thereof.

Claim 3

A circuit for eliminating noise signals from a successiOn of binary bit signals comprising: a pair of channel means for passing bit signals between input and output ends thereof; separate first gating means associated with each of the pair of channel means for delaying the bit signals passed to the associated channel means by a period of time at least equal to the time duration of the noise signals to block noise signals occurring prior to the bit signals from the output end; and separate second gating means associated with each of the pair of channel means for inhibiting the passage of bit signals to the output end of the associated channel means for a selected period of time to block noise signals occurring after the bit signals from the output end; wherein the bit signals are derived from a data signal, the data signal being differentiated to provide a differentiated signal having zero-crossings corresponding to the peaks of the data signal and the differentiated signal being squared to provide a squared signal having bit indicating transitions of substantial slope between opposite signal levels at the zero-crossings thereof which comprise the bit signals, and further including means responsive to the bit signals at the output ends of the channel means for separating the signals into ''''ones'''' and ''''zeros''''.

Claim 4

A circuit for eliminating noise signals from a successiOn of binary bit signals comprising: a pair of channel means for passing bit signals between input and output ends thereof; separate first gating means associated with each of the pair of channel means for delaying the bit signals passed to the associated channel means by a period of time at least equal to the time duration of the noise signals to block noise signals occurring prior to the bit signals from the output end; and separate second gating means associated with each of the pair of channel means for inhibiting the passage of bit signals to the output end of the associated channel means for a selected period of time to block noise signals occurring after the bit signals from the output end; wherein the bit signals are derived from a data signal, the data signal being differentiated to provide a differentiated signal having zero-crossings corresponding to the peaks of the data signal and the differentiated signal being squared to provide a squared signal having bit indicating transitions of substantial slope between opposite signal levels at the zero-crossings thereof which comprise the bit signals, and further including means responsive to the bit signals at the output ends of the channel means for separating the signals into ''''ones'''' and ''''zeros''''.

Claim 5

A circuit for eliminating noise signals from a succession of binary bit signals comprising: a pair of channel means for passing bit signals between input and output ends thereof; means responsive to the bit signals and coupled to the pair of channel means for alternately passing the bit signals to the input ends of the two different channel means; means associated with one of the pair of channel means for delaying the bit signals passed thereto by a period of time at least equal to the time duration of the noise signals to block noise signals occurring prior to the bit signals from the output end; and means associated with both of the pair of channel means for inhibiting the output end of the other one of the pair of channel means for a selected period of time in response to the occurrence of each bit signal in the one of the pair of channel means to block noise signals occurring after the bit signals from the output end of the other one of the pair of channel means; wherein the bit signals are derived from a data signal, the data signal being differentiated to provide a differentiated signal having zero-crossings corresponding to the peaks of the data signal and the differentiated signal being squared to provide a squared signal having bit indicating transitions of substantial slope between opposite signal levels at the zero-crossings thereof which comprise the bit signals, and further including means responsive to the bit signals at the output ends of the channel means for separating the signals into ''''ones'''' and ''''zeros''''.

Claim 6

A circuit for eliminating noise signals from a succession of binary bit signals comprising: a pair of channel means for passing bit signals between input and output ends thereof; means responsive to the bit signals and coupled to the pair of channel means for alternately passing the bit signals to the input ends of the two different channel means; means associated with one of the pair of channel means for delaying the bit signals passed thereto by a period of time at least equal to the time duration of the noise signals to block noise signals occurring prior to the bit signals from the output end; and means associated with both of the pair of channel means for inhibiting the output end of the other one of the pair of channel means for a selected period of time in response to the occurrence of each bit signal in the one of the pair of channel means to block noise signals occurring after the bit signals from the output end of the other one of the pair of channel means; wherein the bit signals are derived from a data signal, the data signal being differentiated to provide a differentiated signal having zero-crossings corresponding to the peaks of the data signal and the differentiated signal being squared to provide a squared signal having bit indicating transitions of substantial slope between opposite signal levels at the zero-crossings thereof which comprise the bit signals, and further including means responsive to the bit signals at the output ends of the channel means for separating the signals into ''''ones'''' and ''''zeros''''.

Claim 7

The invention defined in claim 3 above, wherein the binary bit signals comprise transitions through zero of the waveform of a modified frequency modulated data signal having a succession of substantially uniform bit cells, the waveform of the data signal having a transition through zero substantially at the midpoint of each bit cell representing binary ''''one'''' and substantially at the leading edge of each bit cell which represents binary ''''zero'''' and which is not preceded by a bit cell having a transition through zero at the midpoint thereof.

Claim 8

The invention defined in claim 4 above, wherein the inhibiting means includes gating means coupled to pass bit signals in the other one of the pair of channel means to the output end thereof except when inhibited, means for generating an inhibit signal of selected duration when initiated, the inhibit signal inhibiting the gating means when generated, and means responsive to the occurrence of each bit signal in the one of the pair of channel means for initiating the inhibit signal generating means to generate an inhibit signal, the inhibit signal being initiated within the bit Cell in which the bit signal occurs and terminating within the immediately following bit cell.

Claim 9

A circuit for eliminating noise pulses from a digital data signal, the data signal having a succession of data and clock bits in the form of transitions between two different levels thereof, comprising: first and second channels having input and output ends; means for combining signals appearing at the output ends of the first and second channels; means for providing the data signal to the input end of the first channel; and means for providing the complement of the data signal to the input end of the second channel; the first and second channels each including first gating means coupled to the output end thereof, means responsive to the signal at the input end thereof for enabling the first gating means whenever the signal at the input end assumes a selected value, means coupled to the first gating means and responsive to the signal at the input end thereof for delaying the signal by a first time period at least equal to the time duration of the noise pulses, means coupled to the first gating means and responsive to the signal at the input end of the channel for delaying the signal by a second time period greater than said first time period, the signal as delayed by the second time period combining at the first gating means with the signal as delayed by the first time period to produce pulses of selected duration in response to transitions of a given sense of the signal at the input end of the channel, second gating means coupled between the first gating means and the output end of the channel, the second gating means being normally enabled to pass pulses from the first gating means to the output end of the channel, and means associated with the second gating means and responsive to each occurrence of a pulse at the second gating means for inhibiting the second gating means for a third time period thereafter.

Claim 10

A circuit for eliminating noise pulses from a digital data signal, the data signal having a succession of data and clock bits in the form of transitions between two different levels thereof, comprising: first and second channels having input and output ends; means for combining signals appearing at the output ends of the first and second channels; means for providing the data signal to the input end of the first channel; and means for providing the complement of the data signal to the input end of the second channel; the first and second channels each including first gating means coupled to the output end thereof, means responsive to the signal at the input end thereof for enabling the first gating means whenever the signal at the input end assumes a selected value, means coupled to the first gating means and responsive to the signal at the input end thereof for delaying the signal by a first time period at least equal to the time duration of the noise pulses, means coupled to the first gating means and responsive to the signal at the input end of the channel for delaying the signal by a second time period greater than said first time period, the signal as delayed by the second time period combining at the first gating means with the signal as delayed by the first time period to produce pulses of selected duration in response to transitions of a given sense of the signal at the input end of the channel, second gating means coupled between the first gating means and the output end of the channel, the second gating means being normally enabled to pass pulses from the first gating means to the output end of the channel, and means associated with the second gating means and responsive to each occurrence of a pulse at the second gating means for inhibiting the second gating means for a third time period thereafter.

Claim 11

A circuit for eliminating noise pulses from a digital data signal, the data signal having a succession of data and clock bits in the form of transitions between two different levels thereof, comprising: first and second channels having input and output ends; means for combining signals appearing at the output ends of the first and second channels; means for providing the data signal to the input end of the first channel; and means for providing the complement of the data signal to the input end of the second channel; the first and second channels each including gating means coupled to the output end thereof, means responsive to the signal at the input end thereof for enabling the gating means whenever the signal at the input end assumes a selected value, means coupled to the gating means and responsive to the signal at the input end thereof for delaying the signal by a first time period at least equal to the time duration of the noise pulses, means coupled between the gating means and the delaying means for providing a pulse of selected duration equal to a second time period to the gating means in response to each transition of a given sense of the signal as delayed by the delaying means, and means coupled to the gating means of the opposite channel and responsive to each pulse of selected duration to inhibit the gating means for a third time period.

Claim 12

A circuit for eliminating noise pulses from a digital data signal, the data signal having a succession of data and clock bits in the form of transitions between two different levels thereof, comprising: first and second channels having input and output ends; means for combining signals appearing at the output ends of the first and second channels; means for providing the data signal to the input end of the first channel; and means for providing the complement of the data signal to the input end of the second channel; the first and second channels each including gating means coupled to the output end thereof, means responsive to the signal at the input end thereof for enabling the gating means whenever the signal at the input end assumes a selected value, means coupled to the gating means and responsive to the signal at the input end thereof for delaying the signal by a first time period at least equal to the time duration of the noise pulses, means coupled between the gating means and the delaying means for providing a pulse of selected duration equal to a second time period to the gating means in response to each transition of a given sense of the signal as delayed by the delaying means, and means coupled to the gating means of the opposite channel and responsive to each pulse of selected duration to inhibit the gating means for a third time period.

Claim 13

A circuit for eliminating noise pulses from a digital data signal, the data signal having a succession of data and clock bits in the form of transitions between two different levels thereof, comprising: first and second channels having input and output ends; means for combining signals appearing at the output ends of the first and second channels; means for providing the data signals to the input end of the first channel; and means for providing the complement of the data signal to the input end of the second channel; the first and second channels each including first gating means coupled to the output end thereof, means responsive to the signal at the input end thereof for enabling the first gating means whenever the signal at the input end assumes a selected value, first delaying means coupled to the first gating means and responsive to the signal at the input end thereof for delaying the signal by a first time period at least equal to the time duration of the noise pulses, second gating means coupled between the first gating means and the first delaying means, and second delaying means coupled between the first delaying means and the second gating means for delaying the signal from the first delaying means by a second time period, the signal as delayed by the second time period combining at the second gating means with the signal as delayed by the first time period to produce pulses of selected duration in response to transitions of a given sense of the signal from the first delaying means.

Claim 14

A circuit for eliminating noise pulses from a digital data signal, the data signal having a succession of data and clock bits in the form of transitions between two different levels thereof, comprising: first and second channels having input and output ends; means for combining signals appearing at the output ends of the first and second channels; means for providing the data signals to the input end of the first channel; and means for providing the complement of the data signal to the input end of the second channel; the first and second channels each including first gating means coupled to the output end thereof, means responsive to the signal at the input end thereof for enabling the first gating means whenever the signal at the input end assumes a selected value, first delaying means coupled to the first gating means and responsive to the signal at the input end thereof for delaying the signal by a first time period at least equal to the time duration of the noise pulses, second gating means coupled between the first gating means and the first delaying means, and second delaying means coupled between the first delaying means and the second gating means for delaying the signal from the first delaying means by a second time period, the signal as delayed by the second time period combining at the second gating means with the signal as delayed by the first time period to produce pulses of selected duration in response to transitions of a given sense of the signal from the first delaying means.

Claim 15

The invention defined in claim 8 above, wherein each of the first and second channels includes means coupled to the first-mentioned gating means of the opposite channel and responsive to each pulse of selected duration to inhibit the first-mentioned gating means for a third time period.

Claim 16

A noise discriminator for eliminating noise pulses from a digital data signal, the data signal comprising a complementary pair of signals representing data and clock bits by transitions between opposite signal levels at the centers and leading edges of selected ones of a succession of arbitrarily defined bit cells, comprising: a pair of symmetrical complementary channels having output terminal means and input terminal means coupled to receive different ones of the complementary pair of signals; and signal summing means coupled to the output terminal means of the pair of channels; each of the pair of channels including a first AND gate having first, second and third inputs and an output, an inverter having an output coupled to the first input of the first AND gate and an input coupled to the input terminal means of the channel, first delay means coupled between the second input of the first AND gate and the output of the inverter, second delay means coupled between the third input of the first AND gate and the input terminal means of the channel, a second AND gate having a first input coupled to the output of the first AND gate, a second input, and an output coupled to the output terminal means of the channel, pulse generating means having an input, and an output coupled to the second input of the second AND gate, the pulse generating means providing a pulse of selected duration to the output thereof in response to a signal at the input thereof, and third delay means coupled between the output of the second AND gate and the input of the pulse generating means.

Claim 17

A noise discriminator for eliminating noise pulses from a digital data signal, the data signal comprising a complementary pair of signals representing data and clock bits by transitions between opposite signal levels at the centers and leading edges of selected ones of a succession of arbitrarily defined bit cells, comprising: a pair of symmetrical complementary channels having output terminal means and input terminal means coupled to receive different ones of the complementary pair of signals; and signal summing means coupled to the output terminal means of the pair of channels; each of the pair of channels including a first AND gate having first, second and third inputs and an output, an inverter having an output coupled to the first input of the first AND gate and an input coupled to the input terminal means of the channel, first delay means coupled between the second input of the first AND gate and the output of the inverter, second delay means coupled between the third input of the first AND gate and the input terminal means of the channel, a second AND gate having a first input coupled to the output of the first AND gate, a second input, and an output coupled to the output terminal means of the channel, pulse generating means having an input, and an output coupled to the second input of the second AND gate, the pulse generating means providing a pulse of selected duration to the output thereof in response to a signal at the input thereof, and third delay means coupled between the output of the second AND gate and the input of the pulse generating means.

Claim 18

The invention defined in claim 10 above, wherein the first delay means delays signals applied thereto for a period of time at least equal to the time duration of the noise pulses and less than half the time duration of the bit cells, the second delay means delays signals applied thereto for a period of time greater than that of the first delay means, and the third delay means and the duration of pulses provided by the pulse generating means are selected so as to inhibit the second AND gate during a portion of the bit cell in which a signal at the output of the second AND gate occurs and during a portion of the immediately following bit cell.

Claim 19

A noise discriminator for eliminating noise pulses from a digital data signal, the data signal comprising a complementary pair of signals representing data and clock bits by transitions between opposite signal levels at the centers and leading edges of selected ones of a succession of arbitrarily defined bit cells, comprising: a pair of symmetrical complementary channels having output terminal means, and input terminal means coupled to receive different ones of the complementary pair of signals; and signal summing means coupled to the output terminal means of the paiR of channels; each of the pair of channels including an AND gate having first, second and third inputs, and an output coupled to the output terminal means of the channel, a first inverter coupled between the first input of the AND gate and the input terminal means of the channel, delay means having an output, and an input coupled to the input terminal means of the channel, first pulse generating means having an output, and an input coupled to the output of the delay means, the first pulse generating means providing a first pulse of selected duration to the output thereof in response to a signal at the input thereof, a second inverter coupled between the second input of the AND gate and the output of the first pulse generating means, and second pulse generating means coupled between the output of the first pulse generating means and the third input of the AND gate in the opposite channel, the second pulse generating means providing a second pulse of selected duration to the corresponding input of the AND gate in the opposite channel in response to the presence of a first pulse at the output of the first pulse generating means.

Claim 20

A noise discriminator for eliminating noise pulses from a digital data signal, the data signal comprising a complementary pair of signals representing data and clock bits by transitions between opposite signal levels at the centers and leading edges of selected ones of a succession of arbitrarily defined bit cells, comprising: a pair of symmetrical complementary channels having output terminal means, and input terminal means coupled to receive different ones of the complementary pair of signals; and signal summing means coupled to the output terminal means of the paiR of channels; each of the pair of channels including an AND gate having first, second and third inputs, and an output coupled to the output terminal means of the channel, a first inverter coupled between the first input of the AND gate and the input terminal means of the channel, delay means having an output, and an input coupled to the input terminal means of the channel, first pulse generating means having an output, and an input coupled to the output of the delay means, the first pulse generating means providing a first pulse of selected duration to the output thereof in response to a signal at the input thereof, a second inverter coupled between the second input of the AND gate and the output of the first pulse generating means, and second pulse generating means coupled between the output of the first pulse generating means and the third input of the AND gate in the opposite channel, the second pulse generating means providing a second pulse of selected duration to the corresponding input of the AND gate in the opposite channel in response to the presence of a first pulse at the output of the first pulse generating means.

Claim 21

The invention defined in claim 12 above, wherein the first pulse generating means comprises a single shot multivibrator.

Claim 22

The invention defined in claim 12 above, wherein the first pulse generating means comprises a second AND gate having a first input coupled to the output of the delay means, a second input, and an output coupled to the second inverter and to the second pulse generating means, a third inverter having an output, and an input coupled to the output of the delay means, and a second delay means coupled between the output of the third inverter and the second input of the second AND gate.

Claim 23

The invention defined in claim 12 above, wherein the delay means delays signals applied thereto for a period of time at least equal to the time duration of the noise pulses and less than half the time duration of the bit cells, and the duration of each of the second pulses from the second pulse generating means is at least equal to one and one-half times the time duration of the noise pulses.