Temperature stable monolithic multiplier circuit

Claim 2

In a monolithic integrated circuit producing an output signal in response to at least one input signal in a processing circuit, the operation of which is controlled by a current (I) supplied by a current supply means, which is controlled by a control voltage, with the output of the processing circuit being dependent upon variations in the beta ( Beta ) of the processing circuit with variations in temperature in accordance with the term ( Beta )/( Beta + k) I, where Beta is the current gain of the processing circuit and k is a constant which is small relative to the magnitude of Beta , an improvement comprising: compensating means for supplying a control voltage to the current supply means, said control voltage varying in accordance with variations in the alpha ( Alpha ) of at least one additional transistor in the compensating means to cause said current (I) to vary with temperature in opposition to temperature-caused variations in the Beta of the processing circuit, cancelling the effects of Beta variations from the output signal produced by the processing circuit.

Claim 3

The combination according to claim 1 wherein the compensating means includes first and second voltage supply terminals; a first voltage divider including a first current source and zener diode means connected together at a junction in series between the first and second voltage supply terminals; second current source means including a first resistance means and a first transistor having base, collector, and emitter electrodes, with the base coupled with said junction and the first resistance means coupled between the emitter of the first transistor and the second voltage supply terminal, and circuit means connecting the collector of the first transistor with the first voltage supply terminal, said circuit means having therein a second junction providing said control voltage, said first transistor comprising said one additional transistor.

Claim 4

The combination according to claim 2 wherein the circuit means connecting the collector of the first transistor with the first voltage supply terminal includes a second current source transistor and at least one compensating transistor each having base, collector and emitter electrodes, the collector-emitter paths of said second current source transistor and said compensating transistor being connected together at a junction in series in the order named between the first voltage supply terminal and the collector of the first transistor with the junction between the collector-emitter paths of the compensating transistor and the second current source transistor comprising said second junction.

Claim 5

The combination according to claim 3 wherein k 3 and the second transistor is a lateral PNP transistor and the first transistor and the compensating transistor are NPN transistors; and further including second voltage divider means connected between the first and second voltage supply terminals with a tap on said second voltage divider means connected to the base of the compensating transistor.

Claim 6

A monolithic integrated circuit multiplier for producing an output which is a product of first and second input voltages and which is subject to variation as a result of changes in temperature including in combination: a first differential amplifier having first and second outputs and first and second inputs; a second differential amplifier having first and second outputs and first and second inputs; means for applying said first input signals to the first and second inputs of the first differential amplifier; means for applying second input signals to the first and second inputs of the second differential amplifier; a third differential amplifier including first and second transistors, each having base, collector, and emitter electrodes; a fourth differential amplifier including third and fourth transistors, each having base, collector, and emitter electrodes; means interconnecting the emitter electrodes of the first and second transistors with the first output of the first differential amplifier; means interconnecting the emitter electrodes of the third and fourth transistors with the second output of the first differential amplifier; first and second diode means for supplying current to the first and second outputs, respectively, of the second differential amplifier; means responsive to a reference voltage for supplying current to the first and second diode means; means for connecting the first output of the second differential amplifier with the bases of the second and third transistors; means for connecting the second output of the second differential amplifier with the bases of the first and fourth transistor; means interconnecting the collectors of the first and third transistors to provide a first multiplier output; means interconnecting the collectors of the second and fourth transistors to provide a second multiplier output, the output signal present on said first and second multiplier outputs being in part a function of said current supplied to the diode means and the Beta of the first, second, third and fourth transistors, where Beta is the current gain of said transistors; means for providing a reference voltage to the currEnt supplying means; and means for varying said reference voltage with variations in temperature to cause the current supplied by the current supplying means to the diode means to be varied in an amount to offset variations in said output produced by variations in the Beta of the first, second, third, and fourth transistors.

Claim 7

A monolithic integrated circuit multiplier for producing an output which is a product of first and second input voltages and which is subject to variation as a result of changes in temperature including in combination: a first differential amplifier having first and second outputs and first and second inputs; a second differential amplifier having first and second outputs and first and second inputs; means for applying said first input signals to the first and second inputs of the first differential amplifier; means for applying second input signals to the first and second inputs of the second differential amplifier; a third differential amplifier including first and second transistors, each having base, collector, and emitter electrodes; a fourth differential amplifier including third and fourth transistors, each having base, collector, and emitter electrodes; means interconnecting the emitter electrodes of the first and second transistors with the first output of the first differential amplifier; means interconnecting the emitter electrodes of the third and fourth transistors with the second output of the first differential amplifier; first and second diode means for supplying current to the first and second outputs, respectively, of the second differential amplifier; means responsive to a reference voltage for supplying current to the first and second diode means; means for connecting the first output of the second differential amplifier with the bases of the second and third transistors; means for connecting the second output of the second differential amplifier with the bases of the first and fourth transistor; means interconnecting the collectors of the first and third transistors to provide a first multiplier output; means interconnecting the collectors of the second and fourth transistors to provide a second multiplier output, the output signal present on said first and second multiplier outputs being in part a function of said current supplied to the diode means and the Beta of the first, second, third and fourth transistors, where Beta is the current gain of said transistors; means for providing a reference voltage to the currEnt supplying means; and means for varying said reference voltage with variations in temperature to cause the current supplied by the current supplying means to the diode means to be varied in an amount to offset variations in said output produced by variations in the Beta of the first, second, third, and fourth transistors.

Claim 8

The combination according to claim 5 further including level shifting circuit means including fifth and sixth transistors, with the fifth transistor being a lateral PNP transistor and the sixth transistor being an NPN transistor, each of the fifth and sixth transistors having base, collector, and emitter electrodes; first current source means; means interconnecting the emitter of the fifth transistor and the collector of the sixth transistor with the first current source means; means for providing a DC biasing potential to the bases of the fifth and sixth transistors; means for connecting the first multiplier output with the emitter of the sixth transistor; and roll-off filter means connected between the emitter of the sixth transistor and the base of the fifth transistor for substantially preventing the passing of high frequency signals from the collectors of the first and third transistors through the base-collector path of the fifth transistor.

Claim 9

The combination according to claim 6 further including seventh and eighth transistors, with the seventh transistor being a lateral PNP transistor and the eighth transistor being an NPN transistor, each of the seventh and eighth transistors having base, collector, and emitter electrodes; second current source means; means interconnecting the emitter of the seventh transistor and the collector of the eighth transistor with the second current source means; means for providing said DC biasing potential to the bases of the seventh and eighth transistors; means for connecting the second multiplier output with the emitter of the eighth transistor; and roll-off filter means connected between the emitter of the eighth transistor and the base of the seventh transistor for substantially preventing the passing of high frequency signals from the collectors of the second and fourth transistors through the base-collector path of the seventh transistor; and means for obtaining output signals from the collectors of the fifth and seventh transistors.

Claim 10

The combination according to claim 5 wherein the means for varying said reference voltage includes a first constant current source coupled in series circuit between first and second voltage supply terminals, said first constant current source including first resistance means and a predetermined number of collector-emitter transistor junctions connected in series between said first resistance means and a reference junction coupled to the means for providing said reference voltage, the number of collector-emitter junctions being selected to cause variations in the reference voltage with temperature in an amount sufficient to cause corresponding variations in the current through the diode means to compensate for changes in the Beta of the first, second, third and fourth transistors with temperature so that the output from the third and fourth differential amplifiers is substantially independent of said Beta and, therefore, is substantially independent of variations in temperature.

Claim 11

The combination according to claim 5 wherein the first current source includes a fifth transistor having collector, base, and emitter electrodes, and the first resistance means is an emitter resistor connected between the emitter of the fifth transistor and the second voltage supply terminal and wherein the means for varying the reference voltage further includes: a second current source and zener diode means connected in series in the order named between the first and second voltage supply terminals; means connecting the base of the fifth transistor to a junction point between the second current sourcE and the zener diode means; a third current source including second resistance means and a sixth transistor having base, collector, and emitter electrodes, with the second resistance means connected in series between the first voltage supply terminal and the emitter of the sixth transistor and the collector of the sixth transistor connected in series circuit with said predetermined number of collector-emitter paths, one of which is the collector-emitter path of the fifth transistor; and means coupled with said series circuit of said fifth and sixth transistors and said first and second resistance means for providing an operating potential for the second current source and the base of the sixth transistor, said operating potential also comprising said reference voltage.

Claim 12

The combination according to claim 9 wherein the series circuit interconnecting the collectors of the first and third current source transistors includes the collector-emitter path of at least one additional transistor, with the number of such additional transistors being selected to provide Alpha compensation for the Beta variations in the signal present on the first and second multiplier outputs.

Claim 13

The combination according to claim 9 wherein the fifth and sixth transistors are of opposite conductivity types.

Claim 14

The combination according to claim 11 further including first and second compensating transistors, each having base, collector, and emitter electrodes, wherein the output signal of the third and fourth differential amplifiers on the first and second multiplier outputs is expressed by the general equation: Vo (k RL)/(Rx Ry I) ( Beta )/( Beta + 3) Vx Vy where Vo is the output voltage, k is a constant, I is the current flowing through the diode means, RL is the load resistor, Rx and Ry are degeneration resistors in the first and second differential amplifiers, Vx and Vy are the two input signals, with the compensation being effected by connecting the collector-emitter paths of the first and second compensating transistors in series in the order named between a first junction with the collector electrode of the sixth transistor and a second junction with the collector electrode of the fifth transistor, and further including means for providing forward biasing potential on the bases of the first and second compensating transistors, with said means for providing said operating potential being coupled with the first junction.

Claim 15

The combination according to claim 18 wherein the second current source includes a seventh transistor having base, collector and emitter electrodes and the sixth and seventh transistors are lateral PNP transistors, with the emitters thereof being connected through emitter resistors to the first voltage supply terminal and the collector of the seventh transistor being connected with the zener diode means, and further the means for providing said operating potential including a substrate PNP transistor having base, and emitter electrodes, with the base electrode thereof being connected to the first junction and the emitter electrode thereof providing said operating potential and being connected to the base electrodes of the sixth and seventh transistors.

Claim 16

The combination according to claim 13 wherein the first and second compensating transistors and the fifth transistor are NPN transistors.

Claim 17

A monolithic integrated circuit multiplier including in combination: a first differential amplifier including first and second transistors, each of the transistors including collector, base, and emitter electrodes, the emitters of the first and second transistors being coupled together at a first input terminal; a second differential amplifier including third and fourth transistors, each of the transistors including collector, base, and emitter electrodes, the emittErs of the third and fourth transistors being coupled together at a second input terminal; means for supplying a first input signal to the first and second input terminals; means interconnecting the bases of the first and fourth transistors at a third input terminal; means interconnecting the bases of the second and third transistors at a fourth input terminal; means for supplying a second input signal to the third and fourth input terminals; level shifting circuit means including fifth and sixth transistors, with the fifth transistor being a lateral PNP transistor and the sixth transistor being an NPN transistor, each of the fifth and sixth transistors having base, collector, and emitter electrodes; first current source means; means interconnecting the emitter of the fifth transistor and the collector electrode of the sixth transistor with the first current source means; means for providing a DC biasing potential to the bases of the fifth and sixth transistors; means interconnecting the collectors of the first and third transistors with the emitter of the sixth transistor; roll-off filter means connected between the emitter of the sixth transistor and the base of the fifth transistor for substantially preventing the passing of the high frequency signals from the collectors of the first and third transistors through the base-collector path of fifth transistor.

Claim 18

A monolithic integrated circuit multiplier including in combination: a first differential amplifier including first and second transistors, each of the transistors including collector, base, and emitter electrodes, the emitters of the first and second transistors being coupled together at a first input terminal; a second differential amplifier including third and fourth transistors, each of the transistors including collector, base, and emitter electrodes, the emittErs of the third and fourth transistors being coupled together at a second input terminal; means for supplying a first input signal to the first and second input terminals; means interconnecting the bases of the first and fourth transistors at a third input terminal; means interconnecting the bases of the second and third transistors at a fourth input terminal; means for supplying a second input signal to the third and fourth input terminals; level shifting circuit means including fifth and sixth transistors, with the fifth transistor being a lateral PNP transistor and the sixth transistor being an NPN transistor, each of the fifth and sixth transistors having base, collector, and emitter electrodes; first current source means; means interconnecting the emitter of the fifth transistor and the collector electrode of the sixth transistor with the first current source means; means for providing a DC biasing potential to the bases of the fifth and sixth transistors; means interconnecting the collectors of the first and third transistors with the emitter of the sixth transistor; roll-off filter means connected between the emitter of the sixth transistor and the base of the fifth transistor for substantially preventing the passing of the high frequency signals from the collectors of the first and third transistors through the base-collector path of fifth transistor.

Claim 19

The combination according to claim 15 further including seventh and eighth transistors, with the seventh transistor being a lateral PNP transistor and the eighth transistor being an NPN transistor, each of the seventh and eighth transistors having base, collector, and emitter electrodes; second current source means; means interconnecting the emitter of the seventh transistor and the collector of the eighth transistor with the second current source means; means for providing said DC biasing potential to the bases of the seventh and eighth transistors; means interconnecting the collectors of the second and fourth transistors with the emitter of the eighth transistor; and second roll-off filter means connected between the emitter of the eighth transistor and the base of the seventh transistor for substantially preventing the passing of high frequency signals from the collectors of the second and fourth transistors through the base-collector path of the seventh transistor; and means for obtaining output signals from the collectors of the fifth and seventh transistors.

Claim 20

The combination according to claim 16 wherein the roll-off filter means include first and second roll-off capacitors and first and second resistance means, respectively, and wherein the biasing potential is applied directly to the bases of the sixth and eighth transistors and is applied through the first and second roll-off capacitors, respectively, to the bases of the fifth and seventh transistors; the first resistance means is coupled between the base of the fifth transistor and the emitter of the sixth transistor; and the second resistance means is coupled between the base of the seventh transistor and the emitter of the eighth transistor.