Read-only memory

Claim 1

A read-only memory comprising, a plurality of conductive rows and columns forming a matrix of insulated conductors, the intersection of said rows and columns determining memory storage locations for logical information, selected groups of said rows being connected together at distinct common outputs, a plurality of diodes connected between selected rows and columns for selectively storing logical information in the read-only memory, one type of logical information being stored by the presence of a diode between a selected row and column and a different type of logical information being stored by the absence of a diode between a selected row and column, means for simultaneously providing a first electrical impulse for selecting one row of each group of rows and means for providing a second electrical impulse for individually selecting a column of said plurality of columns for enabling the simultaneous readout of the logical information stored at a plurality of storage locations represented by the intersection of said selected rows and said selected column, said second electrical impulse providing back-bias of diodes connected to said column, said selected rows of each group of rows representing bit positions in a computer word represented by said selected column, a plurality of sensing means connected to the common output of each group of rows to sense the absence or the electrical backbias of diode means connected between said selected rows and columns when a particular row of each group of rows and a column of said matrix have been selected for simultaneously reading out the stored logical information from the plurality of bit positions comprising a computer word, said absence or electrical back-bias of said diode means between said selected rows and columns preventing current flow between a selected row and column for enabling said first electrical impulse to appear at said sensing means.