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US3673577A Expired / Lapsed US ⏱️ 0.0 years remaining

Process control scanner apparatus

Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1971-01-25
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Granted: 1972-06-27
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Expires: 1991-01-25
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Abstract

Abstract A process control computer scans test points arranged in groups to perform operations in accordance with changes in the states of the test points. The data store of the computer stores the states of the test points as words wherein each work represents a group of test points and the bits of the words represent the test points of the group. A flag resister of the data store comprises a group of bit cells with each bit cell being associated with one of the words. During the scan if the change of state of a test point changes, the associated bit in the data store is changed and the flange bit of the associated word is marked. Thereafter, the computer need only scan those words whose flag bits have been marked.

Inventors

  • 👤 Nils Herbert Edstrom
  • 👤 Goran Anders Henrik Hemdal

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 20:25
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54575; H04Q3/54591

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 358 words
In a process control system including a computer wherein a plurality of test points are cyclically scanned so that binary changes in the states of the test points cause the computer to perform control operations, apparatus for reducing the scanning work load of the computer comprising: a plurality of memory units, each of said memory units being connected to one of said test points and beinG activated to store a binary representation when the associated test point changes state, said memory units being divided into groups wherein each group comprises several memory units; a data store, said data store including a plurality of registers, each of said registers being associated with a different one of said memory unit groups and each of said registers including a plurality of bit positions, each of said bit positions storing a binary representation related to the change of state of one of said test points; means for cyclically sampling said groups of memory units such that all the memory units of a group are sampled simultaneously; means for detecting a change of state of a given test point, as indicated by its associated memory unit within a given group; a first register; means responsive to said detecting means for transferring to said first register the binary representations stored by the given group of memory units wherein a change of state has been detected; a second register; means responsive to said cyclic sampling means and said detecting means for transferring to said second register the contents of the register of said data store which contains the binary representations associated with the given group of memory units whose binary representations have been transferred to said first register; logic means connected to said first and second registers for changing the binary significance of the binary representation stored in a given bit position of said second register only when the binary representation of the corresponding bit position of said first register has a given binary significance to form an updated group word; and means for transferring said updated group word back to the register of said data store associated with said given group of memory units.
Claim 2
Dependent Claim 358 words
In a process control system including a computer wherein a plurality of test points are cyclically scanned so that binary changes in the states of the test points cause the computer to perform control operations, apparatus for reducing the scanning work load of the computer comprising: a plurality of memory units, each of said memory units being connected to one of said test points and beinG activated to store a binary representation when the associated test point changes state, said memory units being divided into groups wherein each group comprises several memory units; a data store, said data store including a plurality of registers, each of said registers being associated with a different one of said memory unit groups and each of said registers including a plurality of bit positions, each of said bit positions storing a binary representation related to the change of state of one of said test points; means for cyclically sampling said groups of memory units such that all the memory units of a group are sampled simultaneously; means for detecting a change of state of a given test point, as indicated by its associated memory unit within a given group; a first register; means responsive to said detecting means for transferring to said first register the binary representations stored by the given group of memory units wherein a change of state has been detected; a second register; means responsive to said cyclic sampling means and said detecting means for transferring to said second register the contents of the register of said data store which contains the binary representations associated with the given group of memory units whose binary representations have been transferred to said first register; logic means connected to said first and second registers for changing the binary significance of the binary representation stored in a given bit position of said second register only when the binary representation of the corresponding bit position of said first register has a given binary significance to form an updated group word; and means for transferring said updated group word back to the register of said data store associated with said given group of memory units.
Claim 3
Dependent Claim 76 words
The apparatus of claim 1 and further comprising a flag register in said data store, said flag register comprising a plurality of bit positions, each of said bit positions being associated with a different group of said memory units, and means responsive to said detecting means for marking with a particular binary representation the bit position of said flag register associated with the given group of memory units in which a change of state was detected.

References Cited (Backward Citations)

US3281793A Cited
US3344406A Cited
US3400374A Cited
US3509539A Cited
US3576541A Cited
US3585599A Cited
US3579200A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-06-27 1975-12-27 1976-06-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-06-27 1979-12-27 1980-06-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-06-27 1983-12-27 1984-06-27 $7700.00 Window Closed / Lapsed

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