Electrical circuit arrangements for converting a variable rate of pulse transmission into a related electrical output quantity

Claim 2

An electrical circuit arrangement comprising a storage capacitor arranged to be charged in response to input pulses applied to the arrangement, timing capacitance means also arranged to be charged in response to said input pulses, said timing capacitance means being further arranged such that, during the periods between successive input pulses, the charge thereon decays at least approximately as a rectangular hyperbola to produce a corresponding reference voltage due to said charge decay, the arrangement further including means responsive, when said reference voltage reaches a certain value, for establishing a discharge circuit through which the charge on said storage capacitor decays during the periods between successive input pulses to cause the value of voltage across the storage capacitor to follow the value of the reference voltage, and means for deriving an output quantity from the storage capacitor in accordance with the level of charge thereon.

Claim 3

An electrical circuit arrangement as claimed in claim 1, wherein said timing capacitance means comprise at least two resistance-capacitance circuit elements which are, in effect, superimposed one on the other such that their respective exponential decay voltages are added to form said reference voltage.

Claim 4

An electrical circuit arrangement as claimed in claim 1, wherein said timing capacitance means comprises a resistance-capacitance circuit in which the charge on a capacitor thereof is arranged to decay through a first value of resistance until the voltage across the capacitor has decayed to a certain valve following which the charge is then arranged to decay through at least a second value of resistance to alter the rate of decay, the resulting voltage which forms said reference voltage thus decays in accordance with at least two different exponential rates in succession.

Claim 5

An electrical circuit arrangement as claimed in claim 1 wherein said timing capacitance means comprises a capacitor and first and second resistance paths with different values of resistance, the arrangement including a potential divider having at least one tap point to which the side of the capacitor at which said input pulses are applied is connected via two series-connected diodes, of which the one nearer the capacitor is poled to conduct current away from the capacitor and the other is oppositely poled, means connecting said first resistance path directly across the capacitor and said second resistance path between the junction of said two diodes and the other side of the capacitor, the diode nearer the capacitor being forward biassed when the voltage across the capacitor is greater than the voltage at said tap point whereby the charge on said capacitor decays through both of said resistance paths until the voltage across the capacitor becomes less than the voltage at said tap point whereupon the diode nearer the capacitor is reverse biassed so that the charge on said capacitor then decays only through said first resistance path.

Claim 6

An electrical circuit arrangement as claimed in claim 1 wherein said timing capacitance means comprises, a capacitor, a potential divider having a tap point which is connected to the side of the capacitor at which said input pulses are applied via the parallel connection of a resistance and a diode which is poled to conduct current away from the capacitor, means connecting one end of the potential divider to the other side of the capacitor so that when the voltage across the capacitor is sufficient to cause the diode to become conductive, the charge on said capacitor will decay at a rate governed essentially by the resistance of the potential divider until the voltage across the capacitor becomes insufficient to keep the diode conducting whereupon the charge on said capacitor will decay at a rate governed by the combined value of the resistance of the potential divider and the resistance in parallel with said diode.

Claim 7

An electrical circuit arrangement as claimed in claim 1 wherein said means for establishing said discharge current for the storage capacitor comprises an emitter follower transistor having its base connected to receive said reference voltage and its emitter connected to the storage capacitor via a diode polarized to be forward biassed when the voltage across the storage capacitor becomes greater than the voltage at said emitter to allow the storage capacitor to discharge through the emitter resistor of the emitter follower transistor, whereby the voltage across the storage capacitor follows the emitter voltage and thus the reference voltage.

Claim 8

An electric circuit arrangement as claimed in claim 1 wherein said timing capacitance means comprises at least two resistance-capacitance circuit elements including respective capacitors which are connected in series for charging in response to said input pulses, one of said capacitors being of smaller value than the other and being connected via a first diode to a first source of clamping voltage to which the voltage across this smaller value capacitor is clamped when said first diode becomes forward biassed due to the charge on said one capacitor, and means connecting the other of said two capacitors via a second diode to a second higher source of clamping voltage to which the voltage across said other capacitor is clamped when said second diode becomes forward biassed due to the charge on said other capacitor, the arrangement further including respective shunt resistive paths across the two capacitors through which the capacitors discharge, respectively, during the periods between successive input pulses, the voltage across said two capacitors In series constituting said reference voltage.

Claim 9

A circuit for deriving an output voltage that is proportional to the frequency of an input pulse train comprising, an input terminal adapted to receive the pulse train, a first capacitor, means for charging said capacitor to a given voltage level in response to each input pulse applied to said input terminal, timing capacitor means connected to the input terminal so as to be charged up in response to each input pulse applied thereto, circuit means coupled to said timing capacitor means for discharging same approximately as a rectangular hyperbola during the period between successive input pulses to derive a corresponding reference voltage, means controlled by the reference voltage for discharging the first capacitor during said period between input pulses when the reference voltage reaches a predetermined voltage level and in a manner such that the voltage across the first capacitor follows the reference voltage, and an output terminal coupled to said first capacitor to derive said proportional output voltage.

Claim 10

A circuit for deriving an output voltage that is proportional to the frequency of an input pulse train comprising, an input terminal adapted to receive the pulse train, a first capacitor, means for charging said capacitor to a given voltage level in response to each input pulse applied to said input terminal, timing capacitor means connected to the input terminal so as to be charged up in response to each input pulse applied thereto, circuit means coupled to said timing capacitor means for discharging same approximately as a rectangular hyperbola during the period between successive input pulses to derive a corresponding reference voltage, means controlled by the reference voltage for discharging the first capacitor during said period between input pulses when the reference voltage reaches a predetermined voltage level and in a manner such that the voltage across the first capacitor follows the reference voltage, and an output terminal coupled to said first capacitor to derive said proportional output voltage.

Claim 11

A circuit as claimed in claim 8 wherein said timing capacitor means comprises a second capacitor connected to said input terminal and said circuit means comprises, a voltage divider connected across a source of voltage, and first and second diodes connected in series with opposed polarities between the second capacitor and a tap point on the voltage divider, the diode closest to the second capacitor being polarized to conduct current when the second capacitor voltage exceeds the voltage at the tap point.

Claim 12

A circuit as claimed in claim 9 wherein said circuit means further comprises a resistor connected between the second capacitor and a second tap point on the voltage divider and said first capacitor charging means comprises means for connecting the first capacitor to said input terminal to be charged up by the input pulses.

Claim 13

A circuit as claimed in claim 8 wherein said timing capacitor means comprises second and third capacitors with different values of capacitance and serially connected to said input terminal, and said circuit means comprises a first resistive discharge path connected in shunt with the second capacitor and a second resistive discharge path connected in shunt with the third capacitor.

Claim 14

A circuit as claimed in claim 11 further comprising first and second clamping diodes connected between said second and third capacitors and first and second points of clamping voltage, respectively, and wherein said first capacitor charging means comprises means for connecting the first capacitor to said input terminal to be charged up by the input pulses.

Claim 15

A circuit as claimed in claim 8 wherein said timing capacitor means comprises a second capacitor connected to said input terminal and said circuit means comprises, a voltage divider connected across a source of voltage, first diode gate means connected between the second capacitor and a tap point on the voltage divider and polarized to conduct current when the capacitor voltage exceeds the voltage at the tap point.

Claim 16

A circuit as claimed in claim 13 wherein said circuit means further comprises first and second resistance discharge paths coupled across said second capacitor and one of which includes said diode gate means.

Claim 17

A circuit as claimed in claim 14 wherein the other resistance discharge path includes a resistor connected between the second capacitor and a second tap point on the voltage divider.

Claim 18

A circuit as claimed in claim 13 wherein a portion of said voltage divider is included in at least one of said resistance paths and the other resistance path includes a resistor connected in parallel with said diode gate means.

Claim 19

A circuit as claimed in claim 16 wherein said first capacitor charging means comprises means for connecting the first capacitor to said input terminal to be charged up by the input pulses.

Claim 20

A circuit as claimed in claim 13 wherein said circuit means further includes a resistor across which the referEnce voltage is developed and said first capacitor discharging means includes a diode connected between the first capacitor and the resistor and polarized to conduct current from the first capacitor to the resistor.