US3693170A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cells
Assignee: BAE Systems Electronics Ltd
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Filing: 1970-11-13
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Granted: 1972-09-19
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Expires: 1990-11-13
Abstract
Abstract An electronic memory cell consists of a bistable and three access paths. Two of the access paths control the state of the bistable. Connected between the two access paths controlling the state of the bistable and the third access path is a M.O.S. transistor whose impedance varies in dependence upon the state of the bistable.
Inventors
- 👤 Alfred Brian Edwin Ellis
- 👤 Colin James Shead
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:02
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356026; H03K3/356052; H03K3/35606
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
256 words
A memory cell comprising, in combination: a bistable circuit having first and second output terminals, one for each of two stable states; first, second and third signal access paths; first selectable low impedance path means for connecting said first and said third signal access Paths to read out one stable state of said bistable circuit and second selectably low impedance path means for connecting said second and said third signal access paths to read out the other stable state of said bistable circuit, said first selectably low impedance path means comprising a first selectable low impedance means controlled by said one output terminal of the bistable circuit and a further selectably low impedance means in series with said first selectably low impedance means, said further selectably low impedance means having an input terminal for rendering such further means selectably of low impedance to read out of the bistable circuit and of high impedance to write in to the bistable circuit, and said second selectably low impedance path means comprising a second selectably low impedance means controlled by said second output terminal of the bistable circuit and said further selectably low impedance means in series with said second selectably low impedance means; and third selectably low impedance path means controlled by said first and said third signal access paths for writing in one stable state to said bistable circuit; and fourth selectably low impedance path means controlled by said second and said third signal access paths for writing in said other stable state to said bistable circuit.
Claim 2
Dependent Claim
256 words
A memory cell comprising, in combination: a bistable circuit having first and second output terminals, one for each of two stable states; first, second and third signal access paths; first selectable low impedance path means for connecting said first and said third signal access Paths to read out one stable state of said bistable circuit and second selectably low impedance path means for connecting said second and said third signal access paths to read out the other stable state of said bistable circuit, said first selectably low impedance path means comprising a first selectable low impedance means controlled by said one output terminal of the bistable circuit and a further selectably low impedance means in series with said first selectably low impedance means, said further selectably low impedance means having an input terminal for rendering such further means selectably of low impedance to read out of the bistable circuit and of high impedance to write in to the bistable circuit, and said second selectably low impedance path means comprising a second selectably low impedance means controlled by said second output terminal of the bistable circuit and said further selectably low impedance means in series with said second selectably low impedance means; and third selectably low impedance path means controlled by said first and said third signal access paths for writing in one stable state to said bistable circuit; and fourth selectably low impedance path means controlled by said second and said third signal access paths for writing in said other stable state to said bistable circuit.
Claim 3
Dependent Claim
174 words
A memory cell comprising, in combination: a bistable circuit having two output terminals, one for each of two stable states; first, second and third signal access paths; first means controlled by said first and said third signal access paths for writing in one stable state to said bistable circuit and second means controlled by said second and said third signal access paths for writing in the other stable state to said bistable circuit; and selectably low impedance path means having write in and read out control and controlled by said first and said second output terminals of said bistable circuit for (a) establishing high impedance between said first and said third and between said second and said third signal access paths when either of said first and second means are operative, (b) establishing low impedance between said first and said third signal access paths when said one stable state is read out and (c) establishing low impedance between said second and said third signal access paths when said other stable states is read out.
Claim 4
Dependent Claim
174 words
A memory cell comprising, in combination: a bistable circuit having two output terminals, one for each of two stable states; first, second and third signal access paths; first means controlled by said first and said third signal access paths for writing in one stable state to said bistable circuit and second means controlled by said second and said third signal access paths for writing in the other stable state to said bistable circuit; and selectably low impedance path means having write in and read out control and controlled by said first and said second output terminals of said bistable circuit for (a) establishing high impedance between said first and said third and between said second and said third signal access paths when either of said first and second means are operative, (b) establishing low impedance between said first and said third signal access paths when said one stable state is read out and (c) establishing low impedance between said second and said third signal access paths when said other stable states is read out.
Claim 5
Dependent Claim
146 words
A memory cell comprising a bistable circuit having two output terminals, one for each stable state; first, second and third signal access paths for writing in and reading out with respect to said bistable circuit; and two selectably low impedance paths, one connected between said first and said third signal access paths and the other connected between said second and said third signal access paths, one of said output terminals being connected to control the state of one of said selectably low impedance paths and the other of said output terminals being connected to control the state of the other of said selectably low impedance paths according to the state of said bistable circuit, wherein the selectably low impedance paths are connected between said first and said third signal access paths and between said second and said third signal access paths via selectably low impedance means.
Claim 6
Dependent Claim
146 words
A memory cell comprising a bistable circuit having two output terminals, one for each stable state; first, second and third signal access paths for writing in and reading out with respect to said bistable circuit; and two selectably low impedance paths, one connected between said first and said third signal access paths and the other connected between said second and said third signal access paths, one of said output terminals being connected to control the state of one of said selectably low impedance paths and the other of said output terminals being connected to control the state of the other of said selectably low impedance paths according to the state of said bistable circuit, wherein the selectably low impedance paths are connected between said first and said third signal access paths and between said second and said third signal access paths via selectably low impedance means.
Claim 7
Dependent Claim
37 words
An associative memory store comprising an array of memory cells each as claimed in claim 1 and connected with common first, second and third signal access paths and common control leads to said selectably low impedance means.
Claim 8
Dependent Claim
54 words
A memory cell as claimed in claim 3 and wherein the selectably low impedance means is common to said two selectably low impedance paths, said two selectably low impedance paths being connected to a common point which is in turn connected to said third signal access path by said common selectably low impedance means.
Claim 9
Dependent Claim
44 words
A memory cell as claimed in claim 5 and wherein said selectably low impedance means is a P-type M.O.S. transistor having its source-to-drain path connected between said common Point and said third signal access path and a control lead connected to its gate electrode.
Claim 10
Dependent Claim
98 words
A memory cell as claimed in claim 3 and wherein said bistable circuit comprises two p type M.O.S. transistors each having a drain load, the gate electrode of one being connected to the drain electrode of the other, and the drain electrode of said one being connected to the gate electrode of the other, two further selectably low impedance paths being provided one connected across the drain load of one of said two transistors and the other across the drain load of the other for setting said bistable to one or the other of its two stable states.
Claim 11
Dependent Claim
81 words
A memory cell as claimed in claim 7 and wherein said further two selectably low impedance paths each comprises two M.O.S. transistors connected with their source-to-drain paths in series across the drain load of one of the active elements comprising the bistable circuit, one of the serially connected two transistors having its gate electrode connected to the third signal access path and the other having its gate electrode connected to an appropriate one of the first and second signal access paths.
Claim 12
Dependent Claim
112 words
A memory cell as claimed in claim 7 and wherein said first mentioned two selectably low impedance paths each comprises a M.O.S. transistor, one having its drain electrode connected to said first signal access path, its source electrode connected to said third signal access path via said selectably low impedance means and its gate electrode connected to one of the active elements comprising the bistable circuit and the other having its drain electrode connected to said second signal access path, its source electrode connected to said third signal access path via said selectably low impedance means and its gate electrode connected to the other of the active elements comprising the bistable circuit.
Claim 13
Dependent Claim
40 words
A memory cell as claimed in claim 9 wherein the gate electrodes of the M.O.S. transistors comprising said first mentioned two selectably low impedance paths are connected to the appropriate drain electrodes of the M.O.S. transistors comprising the bistable circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-19 | 1976-03-20 | 1976-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-19 | 1980-03-20 | 1980-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-19 | 1984-03-20 | 1984-09-19 | $7700.00 | Window Closed / Lapsed |