Two device monolithic bipolar memory array

Claim 2

A stored charge storage cell array for a monolithic memory comprising: a. a plurality of storage cells for storing digital information, the plurality of storage cells being connected to an output terminal means for receiving the stored digital information, b. accessing means connected to the plurality of storage cells for writing the digital information into the plurality of storage cells and for reading the digital information from the plurality of storage cells for reception by the output terminal, c. each of the plurality of storage cells comprising first bipolar and second bipolar interconnected semiconductor devices, the first and second interconnected devices having a parasitic capacitor associated therewith for storing a bit of digital information, d. a common sensing line connected to the output terminal means and to the second device, e. a first input terminal connected to the first device for receiving a write signal, and the parasitic capacitor being charged by the write signal to a first binary state in response to the application of a write signal of a first voltage level, f. the parasitic capacitor being placed in a second binary state in response to the application of the write signal of a second voltage level, g. each of the second devices including a control terminal adapted to receive read control signals, h. the second device being responsive to a read control signal so as to discharge the binary signal representative of a first binary signal from its associated parasitic capacitor, the discharge signal being amplified by the beta gain of the second device so as to generate a read output signal on the common sensing line representative of a first binary signal, i. the first and second devices being interconnected between the first input terminal of the first device and the control terminal of the second device, so as to present a direct electrical path between the first input terminal of the first device and the control terminal of the second device, The direct electrical path being constituted by at least a portion of the first device and a portion of the second device, and j. the first and second devices being responsive to the write and read control signals such that at least one of the first or second devices in a cell is non-conductive during storage cell operation in order to eliminate direct power dissipation losses.

Claim 3

A stored charge storage cell array for a monolithic memory comprising: a. a plurality of storage cells for storing digital information, the plurality of storage cells being connected to an output terminal means for receiving the stored digital information, b. accessing means connected to the plurality of storage cells for writing the digital information into the plurality of storage cells and for reading the digital information from the plurality of storage cells for reception by the output terminal, c. each of the plurality of storage cells comprising first and second interconnected semiconductor devices, the first and second interconnected devices having a parasitic capacitor associated therewith for storing a bit of digital information, d. a common sensing line connected to the output terminal means and to the second device, e. a first input terminal connected to the first device for receiving a write signal, and the parasitic capacitor being charged by the write signal to a first binary state in response to the application of a write signal of a first voltage level, f. the parasitic capacitor being placed in a second binary state in response to the application of the write signal of a second voltage level, g. each of the second devices including a control terminal adapted to receive read control signals, h. the second device being responsive to a read control signal so as to discharge the binary signal representative of a first binary signal from its associated parasitic capacitor, the discharge signal being amplified by the beta gain of the second device so as to generate a read output signal on the common sensing line representative of a first binary signal, i. a substrate for supporting the plurality of monolithic storage cells, j. the second device of each cell being constituted by a monolithic transistor formed on the substrate and having base, emitter and collector regions, a portion of the parasitic capacitor being constituted by the monolithic collector-substrate capacitance of the second device, k. the common sensing line being connected to the collector regions of the second device transistors for providing an output signal, l. the common sensing line being a diffused monolithic line having a relatively low resistivity, m. a portion of the common sensing line being located within the base regions of the second device transistors so as to form a first junction comprised by a base region of one conductivity type and a diffused monolithic line of opposite conductivity type, n. the first junction constituting an additional parasitic capacitor in each cell and adding to the collector-base parasitic capacitor for forming a cumulative parasitic capacitor, and o. the cumulative capacitor being responsive to store the write signal representative of a first binary state.

Claim 4

A stored charge storage cell array for a monolithic memory comprising: a. a plurality of storage cells for storing digital information, the plurality of storage cells being connected to an output terminal means for receiving the stored digital information, b. accessing means connected to the plurality of storage cells for writing the digital information into the plurality of storage cells and for reading the digital information from the plurality of storage cells for reception by the output terminal, c. each of the plurality of storage cells comprising first and second interconnected semiconductor devices, the first and second interconnected devices having a parasitic capacitor associated therewith for storing a bit of digital information, d. a common sensing line connected to the output terminal means and to the second device, e. a first input terminal connected to the first device for receiving a write signal, and the parasitic capacitor being charged by the write signal to a first binary state in response to the application of a write signal of a first voltage level, f. the parasitic capacitor being placed in a second binary state in response to the application of the write signal of a second voltage level, g. each of the second devices including a control terminal adapted to receive read control signals, h. the second device being responsive to a read control signal so as to discharge the binary signal representative of a first binary signal from its associated parasitic capacitor, the discharge signal being amplified by the beta gain of the second device so as to generate a read output signal on the common sensing line representative of a first binary signal, i. a substrate for supporting the plurality of monolithic storage cells, j. the second device of each cell being constituted by a monolithic transistor formed on the substrate and having base, emitter and collector regions, a portion of the parasitic capacitor being constituted by the monolithic collector-substrate capacitance of the second device, k. the common sensing line being connected to the collector regions of the second device transistors for providing an output signal, l. the common sensing line being a diffused monolithic line having a relatively low resistivity, m. a portion of the common sensing line being located within the base regions of the second device transistors so as to form a first junction comprised by a base region of one conductivity type and a diffused monolithic line of opposite conductivity type, n. the first junction constituting an additional parasitic capacitor in each cell and adding to the collector-base parasitic capacitor for forming a cumulative parasitic capacitor, and o. the cumulative capacitor being responsive to store the write signal representative of a first binary state.

Claim 5

A stored charge storage cell array for a monolithic memory as in claim 1 wherein: a. the second device is constituted by a transistor having base, emitter, and collector terminals, and b. the common sensing line being connected to the collector terminals of the second device transistors.

Claim 6

A stored charge storage cell array for a monolithic memory as in claim 1 wherein: a. the accessing means include orthogonal decoders for providing decoder control signals, b. regenerating means being connected at its output to an associated common sensing line in a row or column of the storage cell array and to the orthogonal decoders, c. the regenerating means being responsive to the decoder control signals for conditiOning a selected common sensing line during either a write operation, or during a read-regenerating operation.

Claim 7

A stored charge storage cell array for a monolithic memory as in claim 4 wherein: a. the regenerating circuit means further includes a switchable current source energized in response to decoder control signals during a read operation, and b. a selected storage cell, in conjunction with its associated switchable current source, being operative to clamp the output voltage swing on a common sensing line during a read operation so as to reduce power dissipation losses.

Claim 8

A stored charge storage cell array for a monolithic memory as in claim 1 further comprising: a. a substrate for supporting the plurality of monolithic storage cells, b. the second device of each cell being constituted by a monolithic transistor formed on the substrate and having base, emitter and collector regions, a portion of the parasitic capacitor being constituted by the monolithic collector-substrate capacitance of the second device, c. the common sensing line being connected to the collector regions of the second device transistors for providing an output signal, d. the common sensing line being a diffused monolithic line having a relatively low resistivity, e. a portion of the common sensing line being located within the base regions of the second device transistors so as to form a first junction comprised by a base region of one conductivity type and a diffused monolithic line of opposite conductivity type, f. the first junction constituting an additional parasitic capacitor in each cell and adding to the collector-base parasitic capacitor for forming a cumulative parasitic capacitor, g. the cumulative capacitor being responsive to store the write signal representative of a first binary state, and h. the first semiconductor devices of each cell being constituted by monolithic transistors formed on the substrate.

Claim 9

A stored charge storage cell array for a monolithic memory as in claim 2 wherein: a. the second device transistors of each cell are NPN types, and the common sensing line is an N+ diffused region.

Claim 10

A stored charge storage cell array for a monolithic memory as in claim 6 wherein: a. the first semiconductor devices of each cell comprises a PNP transistor having base, emitter, and collector regions, b. the first input terminal connected to the first device for receiving a write signal being connected to the emitter region of the PNP transistor, c. the base region of the PNP transistor being connected to the collector region of the second device and to the common sensing line and, the collector region of the PNP transistor being connected to the base region of the second device.

Claim 11

A stored charge storage cell array for a monolithic memory as in claim 6 wherein: a. the first semiconductor device of each cell comprises an NPN transistor having base, collector and emitter regions, b. the first input terminal connected to the first semiconductor device for receiving a write signal being connected to the base region of the first NPN semiconductor device, c. the collector region of the first NPN semiconductor device being adapted to receive a data signal, d. the emitter region of the first NPN semiconductor device being connected to the base region of the second semiconductor device transistor, and e. the first NPN semiconductor transistor being operated in an inverse transistor mode for discharging the parasitic capacitor during a read operation.

Claim 12

A stored charge storage cell array for a monolithic memory as in claim 6 wherein: a. the first semiconductor device comprises an NPN transistor having base, collector, and emitter regions, b. the first input terminal connected to the first semiconductor device for receiving a write signal being connected to the base region of the first NPN semiconductor device, c. the emitter region of the first NPN semiconductor device being adapted to receive a data signal, and d. the collector region of the first NPN semiconductor device being connected to the base region of the second semiconductor transistor device.

Claim 13

A stored charge storage cell array for a monolithic memory as in claim 9 further including: a. a common node connected to the emitter region of the first NPN semiconductor device and to the base region of the second semiconductor device, and b. the parasitic capacitor being electrically connected at one of its terminals to the common node and at its other terminal to a fixed reference potential.

Claim 14

A stored charge storage cell array for a monolithic memory as in claim 9 wherein: a. the emitter region of the first NPN semiconductor device is connected to the base region of the second semiconductor device, and b. the parasitic capacitor is electrically connected between the base and collector regions of the second semiconductor device.

Claim 15

A stored charge storage cell array for a monolithic memory as in claim 6 wherein: a. the first semiconductor device is constituted by a unilateral conducting device, b. the unilateral conducting device being connected to the base region of the second device, c. the first input terminal connected to the first device for receiving a write signal being connected to the unilateral conducting device, and d. the parasitic capacitor being electrically connected between the base and collector regions of the second semiconductor device.

Claim 16

A stored charge storage cell array for a monolithic memory as in claim 8 wherein: a. the second device monolithic transistors of each cell are of NPN conductivity.

Claim 17

A stored charge storage cell array for a monolithic memory as in claim 9 wherein: a. the second device monolithic transistors of each cell are of NPN conductivity.

Claim 18

A stored charge storage cell array for a monolithic memory as in claim 10 wherein: a. the second device monolithic transistors of each cell are of NPN conductivity.

Claim 19

A stored charge storage cell array for a monolithic memory as in claim 11 wherein: a. the second device monolithic transistors of each cell are of NPN conductivity.

Claim 20

A stored charge storage cell array for a monolithic memory as in claim 12 wherein: a. the second device monolithic transistors of each cell are of NPN conductivity.

Claim 21

A stored charge storage cell array for a monolithic memory as in claim 13 wherein: a. the second device monolithic transistors of each cell are of NPN conductivity.